SU957218A1 - Function converter - Google Patents

Description

The invention relates to computer technology, and can find application in the formation of functions of an arbitrary form when specifying an argument in a digital code.

A device is known that contains a ⁵ register argument, two blocks of memory multipliers and an adder Cl 3.

A disadvantage of the known device is the inability to reproduce functions of an arbitrary form at a given time section and low accuracy.

The closest technical solution to the proposed one is a functional converter containing a pulse generator connected to the input of the subtracting counter, to the installation input of which the code of the current temporary connection from the input bus or register is supplied through the block of AND elements controlled through the delay element by the decoder subtract counter zero code.

The zero code decoder changes the state of the totalizing counter, the overflow of which resets the device to its original state. The parallel ordinate code of the reproduced curve through the registers is fed to two digital-to-analog converters, the outputs of which are connected to the analog inputs of the digital-to-analog converter: to the digital ones! whose inputs are supplied to the code of the summing counter, and its output is the output of the device [2].

The disadvantage of this device is the reproduction of functions at a given time interval only in the form of a straight line and low accuracy due to the use of three digital-to-analog converters in the device.

The purpose of the invention is to increase the accuracy of the reproduction of functions and expand the functional capabilities of the device by reproducing functions other than a straight line, for example power, exponential, trigonometric, hyperbolic, etc.

This goal is achieved in that an e-converter containing an interval register, first and second ordinate registers, four groups of AND elements, an OR element, a delay element, two counters, a zero decoder, a pulse generator, and the output of the pulse generator connected to the counting the input of the first counter, the output of which is connected through the zero decoder to the input of the delay element and the counting input of the second counter, the overflow of which is connected with the first inputs of the elements And the first, second and third groups, the second inputs.

In FIG. 1 shows a block diagram of one time

2, devices; in FIG. 2. - a graph of the functions (sin x) at a given change interval.

₅ The device 'contains a register of intervals, a group of elements AND an OR element 3, a counter 4, a pulse generator 5, a delay element 6, a zero decoder 7, a counter 8, a register 9 to functions, a group 10 memory blocks, a switch 11, a multiplication block 12, a block 13 subtractions, registers 14 and 15 of ordinates, block 16 of adding the group of elements AND 1719, inputs 20-23 of the converter, output 24 of the converter.

Sign inverter 20 is input to the functional tasks vre- ^z alternating interval, the inputs 21 and 22 of the input job ordinate values vykotoryh connected to inputs of reference _20, the initial conditions the converter elements and the outputs of the first group are connected to first inputs of OR elements, and the input intervals, the output register which is connected to the first inputs of AND elements of the fourth group, the second inputs and outputs of which are connected respectively to the output of the delay element and the second inputs of the OR element, the output of which is connected to the installation m the input of the first counter, the outputs of the elements And the second and third groups are connected to the inputs of the first and second registers of ordinates, respectively, a group of memory blocks, a commutator, a multiplication unit ³⁵ , an addition unit, a subtraction unit and a function register, the recording input of which is connected to the output of the overflow of the second counter, the output of the register of functions is connected to the control inputs of the memory blocks of the group, information, inputs and outputs of which are connected respectively to the output of the bits of the second counter and the input of the switch, the output which is connected to the first input of the multiplication unit, the second input and output of which are connected respectively to the output of the subtraction unit and the first input of the addition unit, the second input of which is connected to the output of the second ⁵⁰ ordinate register and the first input of the subtraction unit, the second input of which is connected to the output of the first ordinate register, the output of the addition unit is connected to the output of the converter, 55 the input of the job type of which is connected to the information input of the function register.

the beginning and end of the time interval, input 23 by the input of the job of the type of functional dependence.

Functional Converter operates as follows.

In the initial state, in the interval register 1 and in the first counter 4 through the input 20 and the group of elements And 17 the code of the initial time interval is recorded, and in the ordinate registers of the given function at the beginning of 15 and at the end of 14 of the time section through the corresponding inputs 22, 21 and the group of elements And 19 and 18, the ordinate codes of the specified function are recorded at the beginning of K _n and at the end of K to the time section.

The ordinate codes of each normirozain function Kf5 <0 ί Kf (1, ί = 1, 2, ... Ν) are once entered at the address into the group of memory blocks 10 ^ -10 ^.

According to the given functional dependence, through input 23, the register of function 9, depending on which part of the given function is generated, permits reading the ordinate codes of the normalized function from the corresponding memory block 10j, j = 1,2, ... Ν.

Upon receipt of pulses from the pulse generator 5 to the input of the first counter 4, in the last value of the time interval code decreases to zero and at the moment of zeroing of the zero code decoder 7 it generates a pulse that, acting through the delay element 6, the group of elements AND 2 and the element OR 3, we restore the state of the first counter 4 by writing the contents of register 2, and also increases the code value of the second counter 8 by one. In accordance with the new state of the second counter 8 from the ordinal code block of the ordinates of the normalized function 10j per block selected by the register 23. 12 of multiplication through switch 11, the next ₅ ordinal code values of the normalized function are supplied. The values of the contents of the ordinates of the function ordinates at the end of 14 and at the beginning of the 15th time section are subtracted in block 13 of subtraction taking into account the sign of each ordinate and the result is sent to the multiplication block 12. The product obtained at the output of the multiplication block 12 is summed in the addition block 16 with the contents of the ordinate register of the function at the beginning of the 15th time section <5. Therefore, at the output of addition block 16 at output 25, at each time interval, the ordinate of the generated function is generated, which at each time interval is obtained by transforming the normalized function in time and in accordance with the specified values of the ordinate of the function at the beginning and at the end of this time section. In the general case, the functions generated in this section can change the sign according to the formula

W ± k _{h +} M + K _k - (+ k _n )] .. ³⁴

After filling the second counter 8, v. E. After the last sample of the normalized ordinate function code at the output of the counter 8 overflows po- ³⁵ is a pulse which permits holding to update the registers 1, 14, 15 and 9, respectively timeslots codes ordinate codes functions at the end and at the beginning of a new temporary section, as well as the choice of the next storage device.

In FIG. 2a shows a graph of one of the normalized functions (sin x)

In FIG. Figure 26 shows a graph ** of the functions generated by the functional generator for various values of the ordinates of the function at the beginning and end of a given time section.

As can be seen from the work of the functional converter, its significant difference from the known one is the ability to reproduce more complex functions than a straight line, $$ for example power, exponential, trigonometric, hyperbolic, etc.

957,218 6

Moreover, the functions are reproduced with any predetermined function values at the beginning and end of the time section, which can also change. This extends the functionality of the device and makes it possible to use it as a high-frequency generator of complex functions for automatic control systems for dynamic tests of the strength of full-scale structures.

The proposed device can work in conjunction with a computer, while the signal at the output of the overflow of the counter 8 is the initiating one for performing the next cycle of calculating the specified function.

Claims (2)

The invention relates to computational technology and can be used in the formation of arbitrary functions when specifying an argument in a digital code. A device is known that contains a register of the argument, two memory blocks of multipliers and an adder Cl1. A disadvantage of the known device is the impossibility of reproducing functions of an arbitrary type at a given time interval and low accuracy. The closest technical solution to the proposed is a functional converter containing a pulse generator connected to the input of the detracting counter, to the installation input of which through the OR element the code of the current time segment from the input bus or register is fed through the block of AND elements controlled through the delay element by the decoder zero code subtractive counter. The zero-code decoder changes the state of the totalizer whose overflow causes the device to reset to its original state. The parallel ordinate code of the reproduced curve through the registers is fed to two digital-to-analog converters, the outputs of which are connected to the analog inputs of the digital-analog converter, to the digital inputs of which the code is fed from the summing counter, and its output is the output of device C2. A disadvantage of this device is the reproduction of functions in a given time domain only as a straight line and low accuracy, due to the use of three digital-to-analog converters in the device. The purpose of the invention is to improve the accuracy of reproducing functions and expanding the functionality of the device by reproducing functions other than a straight line, such as power, exponential, trigonometric, hyperbolic, etc. The goal is achieved by the fact that this converter, containing the interval register, first and second, ordinate registers, four groups of AND elements, OR element, delay element, two counters, zero decoder, pulse generator, the output of the pulse generator connected to the counter input of the first counter, the output of which is connected via a zero decoder to the input of the delay element and the counting input of the second counter, the overflow rate of which is connected to the first inputs of the AND elements of the first, second and third groups, the second inputs of which are connected to the inputs of the initial conditions of the converter, outputs elements of the first group are connected to the first inputs of the elements OR, and the input of the register of intervals, the output of which is connected to the first inputs of the elements and the fourth group, the second inputs and outputs of which are connected Respectively, with the output element of the backplane and the second inputs of the OR element, the output of which is connected to the installation input of the first counter, the outputs of the elements of the second and third groups are connected to the inputs of the first and second registers of the ordinates, respectively, a group of memory blocks, a switch, a smart unit, an addition unit, a subtraction unit and a function register, the recording input of which is connected to the overflow output of the second counter, the output of function register VI is connected to the control inputs of the group memory blocks, informational. the inputs and outputs of which are connected respectively to the output of the bits of the second counter and the input of the switch whose output is connected to the first input of the multiplication unit, the second input and output of which are connected respectively to the output of the subtractor and the first input of the addition block whose second input is connected to the output the second ordinate register and the first input of the subtraction unit, the second input of which is connected to the output of the first register of ordinates, the output of the addition unit is connected to the output of the converter, the input of the function type with one Not with information entry of the function register. FIG. 1 is a block diagram of a device; in fig. 2. - a graph of one of the functions (sin x) at a given time interval. The device contains a register of 1 intervals, a group of elements AND 2, an element OR 3 counter, a generator of 5 pulses, a delay element 6, a decoder 7 zero, a counter 8, a register 9 functions, a TO group of memory blocks, a switch 11, a multiplication unit 12, a subtraction unit 13 , registers 14 and 15 ordinates, block 16 of the addition of a group of elements And 17-19, inputs 20-23 of the converter, output 2 of the converter. Functional transducer input 20, the clock is the time interval input, inputs 21 and 22 are the ordinate value inputs at the beginning and the end of the time interval, input 23 is the input of the function dependency type. Functional Converter works as follows. In the initial state, the code of the initial time interval is recorded in the interval register 1 and in the first if counter, through input 20 and the group of elements 17, and the ordinal registers of the given function at the beginning of 15 and at the end of 14 of the temporary section through the corresponding inputs 22, 21 and groups elements And 19 and 18, the ordinates of the given function are recorded at the beginning of K and at the end of the Cc of the temporary section. The ordinates of each normalized function Kf, {0 4 Kf - L i 1, 2, ... N) are once entered at a address in the group of memory blocks. For a given functional dependence, via input 23, function 9 register, depending on which part of the specified function is generated, allows reading the ordinate codes of the normalized function from the corresponding memory block lOj, j 1,2, ... N. When pulses are received from the generator 5 pulses to the input of the first counter 4, the last value of the time interval code decreases to zero and at the time the zero code decoder 7 sets to zero, it generates a pulse that, through the delay element 6, the group of elements AND 2 and the element OR 3 restoring the state of the first counter k by writing the contents of register 2, and also increases the code value of the second counter 8 by one. In accordance with the new state of the second counter 8 from the memory block selected by register 23, the ordinate codes of the normalized function lOj per block (12 clears through switch 11 are fed the following ordinate code value of the normalized fukntion (-) - Values of the ordinate function registers at the end of I and at the beginning of the 15th time section, the subtraction unit 13 is subtracted, taking into account the sign of each ordinate, and the result is fed to the multiplication unit 12. The product received at the output of the multiplication unit 12 is summed up in the addition unit 16 with the register OP Inatas of the function at the beginning of the 15 time section. Consequently, at the output of block 16 of the output 25, the ordinance of the generated function is formed at each time interval, which in each time section is obtained by transforming the normalized function in time and in accordance with the specified values of ordinates The functions at the beginning and at the end of this time section 8 can generally change the function generated on this section and sign according to the formula Sbtxi (± K) .. After filling the second counter 8, i.e. after sampling the last ordinate code of the normalized function, at the output of the overflow of counter 8, an impulse appears that allows updating in registers 1, 1, 15 and 9, respectively, time slot codes, ordinate codes at the end and at the beginning of a new time segment, and also the choice of the next storage device. FIG. 2a is a graph of one of the normalized functions (sin x). FIG. 26 is a graph of the functions generated by the functional generator for various values; to the ordinate codes of the function at the beginning and end of a given time interval. As can be seen from the operation of the functional converter, a significant difference from the known converter is the ability to reproduce more complex functions than the straight line, for example, power, exponential, trigonometric, hyperbolic, etc. the functions are reproduced with any predetermined values of the function at the beginning and end of the time portion, which can also change. This expands the functionality of the device and makes it possible to use it as a high-frequency generator of complex functions for automatic control systems for dynamic strength tests of full-scale structures. The proposed device can operate in conjunction with a computer, and the signal at the output of the overflow of the counter 8 is initiating to perform the next calculation cycle of the specified function. A functional converter comprising an interval register, first and second ordinate registers, four groups of AND elements, OR element, delay element, two counters, a decoder zero, a pulse generator, the output of the pulse generator connected to the counting input of the first counter, the output of which is connected via the zero decoder to the input of the element for-. the holder and the counting input of the second counter, the overflow output of which is connected to the first inputs of the And / first, second and third elements, the second inputs of which are connected to the inputs of the initial conditions of the converter, the outputs of the AND elements of the first group are connected to the first inputs of the OR element and the input of the interval register whose output is connected to the first inputs of elements AND of the fourth group, the second inputs and outputs of which are connected respectively to the output of the delay element and the second inputs of the OR element, the output of which is connected En with the installation input of the first counter, the outputs of the elements of the second and third groups are connected to the inputs of the first and second ordinates, respectively, characterized in that, in order to increase the accuracy j, a group of memory blocks, a switch, a multiplication unit, an addition block are introduced into it, the subtractor and function register, the recording input of which is connected to the overflow output of the second counter, the output of the function register is connected to the control inputs of the memory blocks of the group, the information inputs and outputs of which are connected respectively to the output of the bits of the second calculus and the input of the switch, the output of which is connected to the first input of the multiplication unit, the second input and output of which are connected respectively to the output of the subtraction unit and the first rebar of the adding unit, the second input of which is "OR the first input of the subtraction unit, the second input of which is connected to the output of the ordinate register, the output of the adding unit is connected to the output of the converter, the input setting the function type of which is connected to the information input of the function register. Sources of information taken into account in the examination 1. USSR author's certificate N ° 622090, class, G О F 7/38, 1978. 2. USSR author's certificate number 398969, cl. G About F 3/00, 1973 (prototype). Vf. f // opffy / fG ffifMmr // F ffifjf ef / If e y / syf / fffjr  / f / 7y r. .ff f. f, - / fff ff, ff d., f