SU942035A1 - Device for computing inverse function - Google Patents

Description

one

The invention relates to computing and can be used in the construction of specialized computing devices.

Computing devices are known for reproducing inverse functions til and t 2.

The disadvantages of the known devices are low computation speed and significant hardware costs.

The most technical entity to the proposed device is a device containing three digital integrators, one of which (the third) is tracking, with the first inputs of the first and second integrators connected to the input of the device, the outputs of the first and second integrators connected respectively to the first and second the inputs of the third integrator, the output of which is connected to the second inputs of the first and second integrators C31.

When calculating the function y - for

L

values of x, approaching zero, the calculation error in the specified device increases dramatically.

The aim of the invention is to improve the accuracy of calculations for X values close to zero.

To this end, a device for calculating the inverse function containing the first, second and third integrators, the device input being connected to the first inputs of the first and second integrators, and the output of the third integrator connected to the second

15 to the input of the second integrator, the fourth integrator, the first, second and third adders, the shift register, P histor correction and switch, are entered, the first and second inputs of the first

20 adders are connected to the outputs of co. responsible first and second integrator, and the output of the first adder is connected to the first input of the third.

integrator, the output of which is connected to the first input of the fourth integrator, and the output of the fourth integrator is connected to the second input of the third integrator, the first and second inputs of the second adder are connected respectively to the device input and the first output of the shift register, and the output of the second adder is connected to the input of the shift register and the first in the third adder, the switch input is connected to the second output of the shift register, and the output is connected to the input of the correction register, the parallel and serial outputs of which are connected respectively to the second input of the fourth integrator, and a second input of the third adder, whose output is connected to a second input of the first integrator, and, a third integrator output is the output device. By introducing new blocks and connections in the proposed device, stability and computational accuracy for X values approaching zero is significantly improved. The drawing shows the functional scheme of the device. The device contains the first, second, third and fourth integrators 1 - C (integrator 3 is the next), first, second and third adders 5-7, shift register 8, correction register 9 and switch 10. The first inputs of integrators 1 and 2 are connected to the device input and the outputs with the inputs of the adder 5, the output of which is connected to the first input of the integrator 3, the output of the integrator 3 is connected to the output of the device, the second input of the integrator 2 and the first input of the integrator 4. The first input of the adder 6 is connected to the input of the device, the second input - with the first exit of register 8, and you running - with the first input of the adder 7 and the input of the register 8. The second output of the register 8 is connected to the input of the switch 10, the output of which is connected to the input of the register 9, the first output of which is connected to the second input of the integrator k, and the second output - to the second input of the sum 7 The output of the adder 7 is connected to the second input of the integrator 1. The operation of the device is as follows. Before starting the calculations, the inputs of the initial values of the integrand functions of the integrators 1,2 and and into register 8 are entered, respectively, the values ff-oi o XC

 UO Chr. Calculating the function

Claims (3)

 starts in the device from the moment of input to the input device of the increments dj. Increments d arrive at the first inputs of integrators 1 and 2 and adder 6.-Pass through adder 6 and accumulate in register 8, increments of d form the current value of variable X, which enters the input of switch 10. In this switch, depending on the values of x a correction factor od is generated, whose value is written to register 9. The value of of is generated close to or equal to x but a multiple of 2, so that x pil X 0.12b, then for example if 0.125 2. From register 9, the value cL parallel code is transmitted to the second input int - and the serial code - to the input of the adder 7, where the value x from the adder 6 is subtracted from it. The difference of.- formed in the adder 7 - X goes to the second input of the integrator 1. From the outputs of the integrator 1 and 2 to the inputs adder 5 receives the increment dx multiplied by the values ot-- x and y, respectively. The resulting sum (x) .dx from the output of the adder 5 is fed to the first input of the next integrator 3. From the output of the next integrator, the increment dy is applied to the second input of the integrator 2 and to the first input of the integrator L. From the integrator output, the increment dy multiplied by The value of ° C is fed to the second input of the following integrator 3. The proposed device realizes the differential equation dy jI (c6 - x) dx - ydx. (1) under given initial conditions, the solution of which is the function y -5. Differential equation (1) corresponds to the difference equation. ", ... th ,,,. Н. ;, ,, on which calculations are performed in the device. The difference scheme (2) should be stable, i.e. have a solution that reduces to solving differential equation (1) with h-50. The stability of the circuit (2) is defined as follows. Imagine (2) in the form V n (2 i -1) i, V d d. I d4 / In the Euclidean space we have, "CH1I12-1-DM-- |:;. |. (If H is about, then from (3) we get r C, where C-exp (w b - ag, -} N J-,, b. Thus, because of the boundedness of the operator R, it follows stability and convergence 12.) By choosing the parameter oL, the boundedness of the operator R is reached, for all xyi. While in the known device ot 1 and the boundedness of the operator has the place is not for all values of Xjj a, b. The method error is equal to f hoC Г, 1 МIL V 2lL3J; i J Therefore, the introduction of the parameter slightly increases the volume of the equipment, but allows you to calculate Nor on the entire variable range for a given accuracy, since the computational scheme of mills with stable and methodological error (-N), the proposed device is intended for use in navigation calculators, digital systems, machine control, works, microcalculators and other electronic equipment. The invention is a device for calculating and inverse. function, containing the first, second, and third integrators, the device input being connected to the first inputs of the first and second integrators, and the output of the third integrator is connected to the second input of the second integrator, so that, in order to improve the accuracy of the calculations, it contains, the fourth integrator, the first, second and third adders, shift register, correction register and switch, while the first and second inputs of the first adder are connected to the outputs of the first and second integrators, respectively, and the output of the first sums torus is connected to the first input of the third integrator, whose output is connected to the first input of the fourth integrator, and the output of the fourth integrator is connected to the second input of the third integrator, the first and second inputs of the second summatr are connected respectively to the input of the device and the first output of the shift register, and the output of the second adder is connected to the input of the shift register and the first input of the third adder, the switch input is connected to the second output of the shift register, and the output to the input of the correction register, parallel and after The output outputs of which are connected respectively to the second input of the fourth integrator and the second input of the third adder, the output of which is connected to the second input of the first integrator, the output of the third integrator being the output of the device. Sources of information taken into account in the examination 1. US patent number Zb + VOPZ, cl. G On, 1971. 2. USSR author's certificate №, cl. G About F 7/38, 1977. 3.Neslukhovsky K.S. Digital differential analyzers. M., Mechanical Engineering, 1968, p. 55, fig. 31.