SU995360A1 - Phase synchronization device - Google Patents

Description

. The invention relates to telecommunication technology and can be used in phase synchronization systems for discrete information transmission devices.

Digital phase synchronization systems are known in which digital samples are used from an analog-to-digital converter located up to the loop of the synchronization system [1].

These devices are complex because they include functional converters, the implementation of which requires a large amount of electronic memory. ’’

A phase synchronization device is known, comprising a phase detector connected in series, a discrete averaging unit, an add-exclude pulse unit and a counter, and a reference frequency generator, the output of which is connected to the inputs of the counted pulses of the phase detector and an add-exclude unit for pulses, as well as a frequency divider 12 ]. 25

The disadvantage of this phase synchronization device is its limited frequency range.

The purpose of the invention is the expansion of the frequency operating range. ^ 0

To achieve this goal, a phase synchronization device containing a phase detector connected in series, a discrete averaging block, an add-exclude pulse unit and a counter, and a reference frequency generator, the output of which is connected to the inputs of the counted pulses of the phase detector and an add-exclude pulse unit and divider frequencies, a pulse former, delay elements, an OR element, and an additional counter connected in series, a code rewriting unit, a memory register, and a block with codes, moreover, the signal input of the phase detector is combined with the input of the pulse shaper, the output of which through the frequency divider is connected to the input of rewriting the memory register, to the first input of the OR element and to the input of the first delay element, the output of which is connected to the control input of the code rewriting unit directly and through the second delay element to the input ' ¹ reset' of the additional counter, to the counting input of which the output of the reference frequency generator is connected, the outputs of the counter are connected to

995360 to the current inputs of the block of matching codes, the output of which is connected to the reference input of the phase detector directly and. through the OR element to the input · ’reset’ ’of the counter.

the structural _ diagram of the proposed device is shown ³ * 'reset' ί ί In the drawing, electrical. royals.

The phase synchronization device comprises a phase detector 1, a discrete averaging block 2, a pulse adding / eliminating block 3, a counter 4 _f 'OR element 5, a code matching block 6, a memory register 7, delay elements 8 and 9, a code rewriting block 10 , ¹ pulse shaper 11, a reference frequency generator 12, an additional counter 13, a frequency divider 14. The phase synchronization device operates as follows.

The entry of the device of this mode of operation of the frequency adjustment is preceded by a preliminary cycle. Long. The duration of this cycle T _о is formed with the help of a frequency divider 14, which is brought to zero before starting work. At the input of the divider hour ^ -25 current 14 receives short pulses from the former 11, synchronous with p. transitions through zero signal.

In this case, ^T 8X <τ ₀ = λ - t ~ ' ⁰ i = -i where gpd is the division coefficient of the frequency divider 14.

^t BX ⁼ x —- transition of the input signal, tex

During this time the pulses output from the oscillator 12 supplied to input additional • counter 13, causing the latter accumulates the number s r £ Λ wherein _about - 12 frequency reference frequency generator. '45

At the end of the time interval t _p , * i.e. at the time of overflow of the frequency divider 14, its output pulse sets the counter 4 and the counter 4 to the zero state of the memory register 7 and 50 through the OR element 5, and after the delay time V _2r provided by the elements 8 and 9, respectively (τ ^ + ΐ-2 <j-) - a census in the memory register 7 of the number hi, · accumulated in the higher digits of the additional counter 13 and the reset of this counter. The number £ ₀ T _{0X cf.} <1) where the number of discarded (unused) rarads of the additional counter 13 is proportional to the average (free from the influence superimposed on the. Adumo signal!) Value of the input signal period T _{ex cf.} This is used to generate the phase of the device phase as follows The pulses of the s.output of the generator 12, passing through the block 3 add-exclude pulses, are fed to the input of the counter 4. At the moment of equality of numbers in this counter and the memory register 7, the block 6 matches 1Q codes and generates a pulse, setting conductive counter to zero again 4. Last 'begins to fill the pulser 12, again fires 6 .sovpadeniya block codes, etc., i.e., the process is repeated. Output pulse repetition period to the coincidence unit 6, ^ORD 8YH ^{T =} f _Q whence, taking into account the number of output chassynchronization

U) [1] we have ^r _Vyh = T _vkhsr .

output frequency

Thus, the signal of the proposed device ^£ o ~ T ^ 7 is equal to the frequency U _BX (t)

The initial phase of the signal generated in this way is corrected using a phase detector 1, a discrete averaging unit 2, block 3 add-exclude pulses by adding (excluding) pulses (depending on the phase detection sign 1 detected by the phase detector U _6x (-t ) and _o (b) in the sequence of output pulses of the generator 12, arriving at the counter 4.

At the end of the preliminary cycle, an additional counter 13 starts measuring the new average value of the input signal period, which is carried out similarly during t _A half periods U _BX (¾), the output pulse of the frequency divider 14 again prepares (dumps) the memory register 7 and writes a new number into it . This process is periodically repeated. That way, the device provides discrete monitoring of the frequency of the input signal, as a result of which more favorable conditions are created for the operation of the initial phase correction circuit.

Due to the absence of a linear conversion of the code into the frequency when generating the output signal, it is possible to avoid uneven succession of the output pulses of the discrete frequency synthesizer (in the proposed embodiment, this role is played by counters 4 and 13, memory register 7, block 6 matching codes and block 10 rewriting codes. at the output of block 6, the coincidences of the codes have a uniform arrangement in time (they follow with a period of 7 input wednesday) · In this regard, there is no need to delet GOVERNMENTAL frequency (the latter is equal to the frequency of the output circuit or the input signal frequency).

Thus, when using the same elemental base as in the high-voltage device, it becomes possible to increase the upper boundary of the frequency range of the proposed device.

Claims (2)

. The invention relates to telecommunications engineering and can be used in phase synchronization systems for discrete information transfer devices. lisBecTHH digital phase synchronization systems that use digital samples from an analog-to-digital converter that is up to the loop of the synchronization system 1. These devices are difficult because they include functional converters that require a large amount of electronic memory, A phase synchronization device is known comprising a series-connected phase detector, a discrete averaging unit, a pulse exclusion addition unit and a counter, and the same reference clock generator The frequency of the output is connected to the inputs of the counting pulses of the phase detector and the addition and removal unit, as well as the frequency divider 12. A disadvantage of this phase synchronization device is its limited frequency range. The purpose of the invention is to expand the frequency of the working range. To achieve this goal, a phase synchronization device containing a series-connected phase detector, a discrete averaging unit, a pulse addition and exclusion unit and a counter, and a reference frequency generator, the output of which is connected to the inputs of the phase pulses and the pulse addition and exclusion unit frequency divider, cc; there is a pulse shaper, delay elements, an OR element and an additional counter connected in series /; the code rewrite unit, the storage register and the code coincidence unit, the signal input of the phase detector is combined with the input of the pulse generator, the output of which is connected via the frequency divider to the rewriting input of the evaporative register, to the first input of the delayed element, which is connected to to the control input of the code rewriting unit directly and through the second delay element to the input a reset of the additional counter, to the counting input of which the output of the generator is connected simplicity, the counter outputs are connected to inputs of block codes sootvetstvugatsim coincidence / output of which is connected to the input poles Nome phase detector and directly. through the element OR to enter the reset counter. The drawing shows a structural electrical circuit of the proposed device. The phase synchronization device contains a phase detector 1, a discrete averaging unit 2, a unit 3 for adding pulse exclusion, a counter Element OR 5, a block 6 for a Kodo memory register 7, elements 8 and delays, a block 10 for rewriting codes, a driver 11 for pulses reference frequency generator 12, additional counter 13, frequency divider 14. The phase synphonization device operates as follows. The entry of a device given in the frequency control mode is preceded by a preliminary cycle. The duration of this cycle, tj, is formed by the frequency divider 14, given before the start of the cycle, to the zero state. At the input of divider 14, short pulses are received from the forcher 11, which are synchronous with transitions through the signal zero (t}. At the same time, T ex exi about C – Hgddet - the division factor of the frequency divider 14. 1. In - the input signal During this time, the pulses from the output of the generator 12 arrive at the additional input of the counter 13, resulting in the latter accumulating the number N, -r;, € o, where fn is the frequency of the reference frequency generator 12. At the end of the time interval T t. that is, at the time the frequency divider overflows, its output pulse is carried out setting to zero with the storage register 7 and counter 4 through the element OR 5, and after the delay time tfg, provided by elements 8 and 9, respectively (T + Ca, the census 7 of the number stored in the high-end bits counter 13 and the reset of this counter. The number of S –R– r t Td p. (1.) where. h is the number of discarded (non-usable) bits of the additional counter 13, proportional to the average (free from the influence of the signal lavMosi value of the period of the input signal This number is used to form The output frequency of the phase synchronization device is as follows. The pulses from the generator 12 output, passing through the block 3 of adding and excluding pulses, are fed to the input of counter 4. At the moment of equality of the numbers in this counter and the storage register 7, the block 6 of code matching is triggered and generates a pulse, setting the counter to zero again. starts to be filled with generator pulses 12, again, block 6 matches codes, etc., i.e. the process is repeated. The period of the output pulses of the block b matches the codes. N out f from / / taking into account 1 we have out yr. thus, the output signal frequency of the proposed device is equal to the frequency Oex (t). The initial phase of the signal generated in this way is corrected with the help of phase detector 1, discrete averaging unit 2, unit 3 for adding and excluding pulses by adding (excluding) pulses (depending on detected by the phase detector 1 of the phase mismatch sign) and Um, (- t) in the sequence of output pulses of the generator 12 arriving at the counter 4. At the end of the preliminary cycle, additional counter 13 begins The measurement of the new average period of the input signal, which is carried out similarly during the t half-periods Ugw (.t), the output pulse of the frequency divider 14 again prepares (resets) the storage register 7 and rewrites the new number into it. This process is periodically repeated. In this way, a discrete tracking of the input signal Uex is performed in the device, resulting in more favorable conditions for the operation of the initial phase correction circuit. Due to the absence in the device when forging the output signal of a linear conversion of a code into a frequency, it is possible to avoid unevenness of the output pulses of the synthesizer of discrete frequencies (in the proposed embodiment, this role is performed by counters 4 and 13, the memory register 7, block 6 of code match, and block 10 of code transfer. The pulses at the output of the block b of coincidence codes have a uniform distribution in time (followed by a period of fgx sr). In this connection, there is no need to divide the output frequency of the synthesizer frequencies (the latter is equal to the output frequency of the circuit or the frequency of the input signal.) Thus, using the same element base as in the known device, it becomes possible to increase the upper limit of the frequency range of the proposed device. Formula of the device The phase synchronization device containing series-connected phase a detector, a discrete averaging unit, a pulse addition and pulse counter and a counter, as well as a reference frequency generator, the output of which is connected to the inputs even-num pulses of a phase detector and an add-exclude pulses unit and a Frequency splitter, which has been used, that, in order to expand the frequency of the working range, a pulse driver, E13 delays, element OR and in series connected additionally a counter, a code rewriting block, a dganr | Mynayu1tsiy register and a block of matching codes, the signal input of the phase detector combined with the input of the pulse former, the output of which is divided into frequency, the frequency is connected to the rewrite input memory register, to the first input of the OR element and to the input of the first delay element, the output of which is connected to the control. input of the code rewriting block directly and through the second delay element to the input reset of the additional counter, the counting input of which is connected to the output of the reference frequency generator, outputs of the counter connected to the corresponding inputs of the code match block, whose gateway is connected to the supporting input of the phase detector directly and through the malicious OR to the reset counter input, Sources of information / reception Tye into account during the examination 1. Zhodzishski M.I. Digital systems Mt3 phase synchronization. - Radio engineering and electronics, 1979, v.24, 9, p. 1786. 2. Zhodzishsky M.I. and other Calculation models. Digital systems FAP. -Let VUZDV USSR, electronics. 1976, t. 19, 3, p. 43 (prototype). Vfym t / gtiffi) // /four  Mr. J i) t  . n I fj