SU995299A1

SU995299A1 - Pulse discriminating device

Info

Publication number: SU995299A1
Application number: SU813267338A
Authority: SU
Inventors: Александр Григорьевич Бирюков; Валерий Иванович Медведев; Владимир Алексеевич Маслов
Original assignee: Предприятие П/Я А-7309
Priority date: 1981-02-16
Filing date: 1981-02-16
Publication date: 1983-02-07

Description

Изобретение относитс к импульс:ной технике и может быть использовано в устройствах автоматики,, вычислительной и измерительной техники.The invention relates to a pulse: Noah technique and can be used in automation devices, computing and measuring equipment.

ИзвестнЪ устройство дл выделени первого, шлпульса из„..серии, содержащее Чшину сигналов управлени шину последовательностей импульсов, 1К-триггер и элемент И-НЕ,соединенный одним из входов с шиной последовательнрсти импульсов и синхровходом 1К-триггера,выход которого соединенсо входами 1 и К триггера и входом элемента H-HE{ I.A device for isolating the first, shlpulse from the ".. series" is known, which contains the Tire of control signals of a pulse train, a 1K trigger, and an NAND element connected by one of the inputs to the pulse train and a 1K trigger trigger, whose output is connected with inputs 1 and To trigger and input element H-HE {I.

.Однако при совпадении импульса входной последовательности с импульсом управлени происходит искажение его длительности.However, when the pulse of the input sequence coincides with the control pulse, its duration is distorted.

Наиболее близким техническим решением к. предлагаемому вл етс устройство , содержащее инвертор, вход которого соединен с nepSiiM входсш второго элемента И-НБ, а выход инвертора подключен через первый элемент и-НЕ к. единичному входу первого триггера, выход которого ;Через . второй элемент И-НЕ соединен с единичным входом триггера. Первый вход дополнительного элемента И-НЕ соединен с.выходом второго триггера, а ее .The closest technical solution to the proposed is a device containing an inverter, the input of which is connected to the nepSiiM input of the second I-NB element, and the output of the inverter is connected via the first element I-NOT to the single input of the first trigger, the output of which; the second element is NOT connected to a single trigger input. The first input of the additional element AND is NOT connected to the output of the second trigger, and its.

второй вход.- с единичным входом этого .триггера. Выход дополнительного , элемента И-НЕ подключен к второму входу jnepBoro элемента И-НЕ и второму входу.первого триггера. Третий вход первого элемента Л-ИЦ соединен с вторым.входом второго триггера 2} .the second input. - with a single input of this .trigger. The output of the additional, AND-NAND element is connected to the second input of the jnepBoro NAND element and to the second input of the first trigger. The third input of the first element L-IC is connected to the second input of the second flip-flop 2}.

Недостатком известного устройства The disadvantage of the known device

10 вл етс сложность и необходимость : установки триггеров схемы в исходное состо иие перед иачгшом работы.10 is the complexity and necessity: setting the triggers of the circuit to its original state before the initial work.

Цель изобретени - повышение точности вьщелени широтикос импульсов The purpose of the invention is to improve the accuracy of the width of the pulse width

15 при одноврв4енном .упрс дении устройст ва , . . -г-- - ...15 at the same time. Device management,. . -r-- - ...

Поставленна цель достигаетс тем, что .в устройстве дл выделени импульсов , содержащем первый и второй This goal is achieved by the fact that in the device for the selection of pulses, containing the first and second

20 элементы И-НЕ, инвертор , RS-триггер , инфсфмационную шину и шину управлени , .соединенную с первым входом первого элемента И-НЕ, выход которого соединен с первым входом RS-триг25 гера, соединенного выходом с. первым входом второго.элемента И-НЕ, а второй вход второго элемента.И-НЕ соет динен .с информационной шиной, вход инвертора .соединен с первым входом 20 elements AND-NOT, inverter, RS-trigger, information bus and control bus connected to the first input of the first AND-NOT element, the output of which is connected to the first input of the RS-trigger 25 connected by the output c. the first input of the second element is NAND, and the second input of the second element. AND-NOT connects the information bus, the input of the inverter is connected to the first input

Claims

30 jiepBoro element IS-NOT, and the output with the third input of the second element AND-NOT while the second input of the RS flip-flop is connected to the second, the inputs of the first and second elements AND-YE, FIG. 1 is a functional electrical circuit of the device for selecting pulses; 2 and 3 are timing diagrams. The device includes a control bus 1, information bus 2, the first AND-HE circuit 3, inverter 4, trigger 5 and the second element 6 AND-NOT, output bus 7, block 8. The device can operate in various modes, for example, in the selection mode one pulse from the input sequence, the selection of a pack of pulses, the selection of pulses according to a given program, etc. Consider, for example, the selection of a single pulse and a burst of pulses in the non-input sequence, and the sequence of pulses can be either regular or irregular. In the initial state, when a series of HMjiyjibs is extracted from the series, a high potential is supplied to bus 1, which through inverter 4 feeds from the third input of the AND-NOT 6 element, thus, regardless of the state of the rest of the circuit elements, impulses from the information bus 2 the output of the NAND element is not passed. At the moment of time t. the bus receives an enable signal in the form of a logical difference from "i" to 0 "It is possible that at this moment there is an information pulse on bus 2 but it is output to the output of the I- NOT b does not pass, since the trigger 5 at the time moment of Dust It is introduced in the low level from the element AND-NOT 3, at the input of which at the moment t high levels, i.e. 1, Thus, at the first input of element b, at the moment of time C, there is a low level from trigger 5, and it does not pass the pulse coming from bus 2. After the termination of the pulse from bus 2 at time b, trigger 5 is set to zero state (Q 1) low through bus 2, resulting in the arrival of the next impulse from data bus 2 on the first and third inputs of the NANDO element there are high potentials. The impulse that arrives at time tj from the information bus 2 without any distortion passes to the output of the element AND NOT HE. . Block 8 can either be a counter or a software sampling device for measured pulses, etc., (prohibit the passage of the following pulses on the falling edge of a pulse transmitted through an IS-NOT element b. If time t coincides with the pause on bus 2, then operation of the device is further simplified, since the trigger 5, set low by bus 2 to the zero state (), prepares element 6 for IS-NOT to pass the first pulse (after being resolved) over bus 2. In Fig. 3 plots are shown. voltage of a dedicated burst. a device that, in this mode, is similarly predictive, only block 8, representing, for example, a counter, generates a inhibit impulse after passing a predetermined number of impulses along bus 2 to the output of the AND-N element. Thus, regardless of the time when the resolution impulse arrives devices receive a pulse or a burst of impulses of a non-distorted duration, which is very important for measuring devices using systems that use amplitude-time converters, or when measuring the duration of an electric pulse catch. The proposed device favorably differs from its analogs by the simplicity and reliability of pa6oTti. With the help of the proposed scheme, one pulse can be distinguished, a burst, or pulses can be extracted according to a program, which greatly expands the possibilities of its application. The invention The device for the selection of pulses, containing the first and second elements AND-NOT, inverter, RS-flip-flop, information bus and control bus connected to the first input of the first AND-NAND element, the output of which is connected to the first input of the RS-flip-flop connected to the output the first input of the second element IS-NOT, and the second input of the second element IS-NOT connected to the information bus, which is so that, in order to improve the accuracy of the selection of latitudinal pulses while simplifying the device, the input of the inverter is connected with n The first input is the first NAND element, and the output is with the third input of the second NAND element, while the second input of the ks-flip-flop is connected to the second inputs of the first and second NAND elements. Sources of information, accepted attention in the examination 1. Avtorskoe SBiedele.StBO USSR № 5729I, KL..N 03 K 5/19, 01.10.74.

2. USSR Author's Certificate No. 4G4070, .cl. H 03 K 5/13, 06.02.73.

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