SU995289A1 - Cycle generator - Google Patents

Description

(54) CYCLSSH GENERATOR

I

The invention relates to a pulse technique and is intended to generate 4-pulse signals with a predetermined follow-up period.

A device for generating pulse bursts is known, comprising a multi-pulse pulse generator, a multivibrator, a binary counter and a decoder, a switch in the form of a push-button switch, a clock pulse generator, binary counters. pulses, delays with decoders. Delay sensor, implemented on a multivibrator with a synchronizing input for external triggering, keys, triggers, AND, OR II elements.

A significant disadvantage of the device is that the pulses in a burst are generated at a generator frequency of 20 clock pulses, i.e. the tuning range of the period following the output pulses is limited.

The purpose of the invention is to expand the functionality by expanding. 25 widths of the tuning range of the pulse following period.

The goal is achieved by the fact that in the cycle generator containing the synchronization unit, the main register 30

memory, code tuning unit, the OR element, the reference frequency generator, the input of which is connected to the first input of the synchronization unit, the second input of which is connected to the output (1 reference frequency generator, the third input of the synchronization unit is connected to the output of the OR element, a parallel accumulator is entered, an additional memory register, an OR block, two NAND elements, the inputs of the accumulating parallel sumatrr are connected to the outputs of the code adjustment block, the inputs of which are connected via the OR block of inputs The data of the main memory register are connected to the outputs of the accumulating parallel adder, the synchronization input of the accumulating parallel adder is connected to the first output of the synchronization unit, the second output which is connected to the second inputs of the element block, OR, the third output is connected to the first input cm of the first NAND element, the output of which is connected to the input wasp, the main memory register, the second input is connected to the fourth output of the synchsonietier unit, the synchronization input of the additional memory register and the first input of the second AND-NOT element, the second input of which is connected to the output of the reference frequency generator and the transfer input of the accumulator parallel parallel adder, and the output is connected to the fourth input of the synchronization unit and the reset input of the additional memory register. The drawing shows a structural diagram of a cycle generator. The cycle generator contains a TOD I generator of the reference frequency, a code adjustment unit 2 consisting of g of decimal keyboard keys, each of which has ten keys, one input and four inputs accumulating a parallel adder 3, having m inverted transfer outputs of the oldest digit of each tetrads, main register 4 shifts on KZ-triggers, additional register 5 shifts ha on D-triggers, block 6 of elements OR, element OR 7, elements AND-HE 8 and 9 ,. a synchronization unit 10, which consists of delay elements 11 and 12, a D-flip-flop 13, a single pulse extraction unit 14. The drawing also shows the start-up bus 15 and the exit to the bus 16. The principle of operation of the cycle generator is to follow. (The generator 1 of the reference frequency generates signals with a frequency, f, which are fed to the synchronization inputs of the D-flip-flop 13 and the block 14 for selecting a single pulse of the block 10, the inverse input of the IS-NE element 8, through the delay element 11 of the inverted input of the And- element NOT 9, to the transfer input of the mattress 3 and through the elements 11 and 12 of the delay to the synchronization input of the adder 3. The delay of the elements 11 and 12 is determined by the time of the establishment of the Transient processes in the adder 3 and its input circuits. case in parallel binary mode combi-accumulating type adder having a group of inputs for receiving the binary code of the second term formed in the tuning unit 2 based on signals from the outputs of the block 6 of the OR elements. The first term is stored in the adder 3, the Tuning block 2 provides for setting the decimal code To the size of m in order to tune the cycle generator to a given frequency f, which differs from the reference frequency f by an amount determined by the expression. n Uo-Ki) where K is a digit in the 1st digit of the decimal code K. The installation of the decimal code K is made using the corresponding keys on the key combs of block 2, the output of which forms the tetrads of the binary-decimal Code. The correspondence between the decimal key designation and the resulting binary code in the tetrad is as follows. The reference frequency generator 1 is started up by a start signal supplied via the device bus 15 as a logical unit during the entire cycle generator operation time. After the start signal arrives at the control input of block 14 of block 10, a single pulse is generated at the output of the latter based on the first signal of the reference frequency f, which through the block of b elements OR, in accordance with the set values on the keys of the tuning block 2, forms the initial code of binary numbers transmitted via parallel buses to the input of the adder 3. The adder 3, previously set to the zero state, performs a binary summation of the received initial code with a single value from the input the nose at the sync input signal and remembers the result of the summation. The second and subsequent signals from the generator 1 of the reference frequency with the preserved start signal block 14 does not generate pulses at the output, therefore, provided there is no transfer from the highest bit of any tetrad in the previous summation cycle, the initial code from the output of block 2 to the input of the adder 3 will not be received , and the number in the adder will be summed up with a single value from the transfer input and the result will be accumulated in adder 3. This will continue until at least one of the two is overflowed. hell. In this case, the transfer signal from the highest bit of this tetrad goes through the corresponding inverse output of the adder 3 to the input of the unit in the unit state of the corresponding trigger register 4 is stored in it and transmitted to the information input of the corresponding p-trigger register 5, and through the element OR 7 to the informational input of b-flip-flop 13 block 10.

The next signal from the generator 1 p-flip-flop 13 is set to a single state, the output of which rewrites the signal of the transfer into the corresponding D-flip-flop register

5, and through the IS-HE element 9, on the inverse input of which the signal from generator 1 is delayed by the holding element 11, setting the RS-triggers of register 4 to the zero state, thereby preparing them for receiving the following transfer signals or adder 3. S c the output of the corresponding DT register register 5 goes through block 6 of the elements OR to block 2 of the adjustment to form the initial code to restore the overflowing tetrad. The adder 3 performs a binary summation of the result accumulated in it from the input signal. The input transfer code and the initial code of the corresponding tetrad as the second term were recorded, and the result was accumulated further. The end of action of the aforementioned signal from the output of the generator 1, the output signal of the NAND element 8 sets the zero state of the D-flip-flops of register 5 and. D-flip-flop 13 of block 10. The process of accumulating the result in adder 3 continues until all m binary-decimal tetrads are refilled while the adder 3 is set to the zero state, transfer signals from all tetrads are prepared for recovery the initial code of the second term, and on the device bus 16, an output signal appears, formed on the last triggers of registers 4 and 5, on a base. transfer signal from the higher tetrad. .

In the next cycle of generating the output signal, the cycle generator works in a similar way.

After the start signal has been removed from the bus 15, all the cycle generator nodes containing the storage elements are set to the zero state. The circuits for setting to the initial zero state are not shown in the diagram.

The proposed generator provides a reliable restoration of the initial code — any tetrade or combination of tetrads, which complement the decimal code K specified by the tuning block, in accordance with the transfer signals cy

The mat, while adjusting the output frequency of the output signals is very simple and is provided by setting the decimal code K in the tuning block. The signal at the output of the cycle generator can be obtained over the entire tuning range, starting with the value of the reference frequency f to the value set with the tuning block. This eliminates a significant drawback of the known cycle generators, in which the output signal cannot be obtained in the frequency range (f - f / 4m). In the proposed generator, the functionality is extended.

Claims (1)

1. USSR author's certificate 822325, cl. H 03 K 3/64, 1979.