RU1783526C - Random member generator - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to expand the functional capabilities by generating random numbers with a Poya distribution. The generator contains a GTI 1, delay elements 2.14, keys 3.10, accumulating adders 4, 11, an adder 5, a division unit 6, a comparison unit 7, a counter 8, 12, a register 9, an OR element 13, a sensor 15 of uniformly distributed random numbers. 1 ill.

Description

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The invention relates to computer technology and can be used to generate random numbers with a Poia distribution.

A disadvantage of the known device is its relatively narrow functionality, since it does not allow the generation of random numbers with a Poya distribution.

The purpose of the invention is the expansion of functionality.

The drawing shows an electrical structural diagram of a generator.

The random number generator contains a serially connected clock pulse generator (GTI) 1, a delay element 2, a key 3, an accumulating adder 4, an adder 5, a division unit 6, a comparison unit 7, a counter 8 and a register 9, a key 10 in series, the information input of which is connected connected to the output of the delay element 2, and the accumulating adder 11, the output of which is connected to the second inputs of the adder 5 and the dividing unit, connected in series with a counter 12, the input of which is connected to the output of the GTI 1, the OR element 13, the second input of which is connected is connected with the input of the GTI 1, and the output with the control input of the register 9 and with the control input of the initial installation accumulating adders 4 and 11 and a delay element 14, the output of which is connected to the installation input to zero of the counter 8, as well as the sensor 15 evenly distributed random numbers (DRRSCH), the input of which is connected to the output of the GTI 1, and the output to the second input of the comparison unit 7.

The generator is based on a method of generating random numbers with a Poia distribution.

According to the start-up pulse, the GTI starts to generate a sequence of pulses, and the accumulating adders update their contents to the initial states and (1-P), respectively, where, and mi °, GP2 are integers.

Then, at the output of block 6, taking into account the summation of mi ° and rn2 ° in adder 5, the relation

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which is compared with the possible value of a random number r having a uniform distribution and formed at the output of the DRRS by the polling pulse of the GTI 1 supplied to its input. If, then a signal with the level of a logical unit of

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is activated at the second output of block 7, which is supplied to the control input of the second key 10, otherwise, at the first output of block 7, which leads to the opening of the first key 3. In the first case, the signal from the output of comparison block 7 allows the counter 8 to be counted and its informational input is the next GTI pulse 1. The same pulse passes through the key 3 and a constant integer S is added to the contents of the accumulating adder 11. The processes described above are repeated.

If the signal of the logical unit is generated at the first output of the comparison unit 7, which is supplied to the control input of the key 3, then, according to the pulse of the GTI 1, the integer S is added to the contents of the accumulating adder 4, and the counter 8 does not change its state.

The processes described above are repeated until a pulse occurs at the overflow output of the counter 12, designed for n pulses. According to this pulse, the contents of counter 8 are transferred to register 9, which is a possible value of a random number with a Poia distribution. At the same time, the contents of accumulating adders are updated, and after a short delay in delay element 14, a new cycle begins when the information is transferred to register 9. generating a number with a Poia distribution.

Claims (1)

The claims A random number generator comprising a first counter, a register whose output is the output of the generator, first and second keys, a comparison unit, an adder, a division unit, a first accumulating adder, an evenly distributed random number sensor, two delay elements and an OR element, the first input of which is the start input of the generator, and the output is connected to the input of the first delay element, the output of the first counter is connected to the information input of the register, the output of which is the output of the generator, the outputs are Greater than or equal to Less e comparison units are respectively connected to the control inputs of the first and second keys, characterized in that, in order to expand the functionality by generating random numbers with a Poya distribution, a second accumulating adder, a second counter and a clock generator are introduced into it, the trigger input of which connected to the start input of the generator, and the output is connected to the start input of the sensor evenly distributed random numbers, to the counting input lane. 5 17835266 ftoro of the counter, to the information input it is connected to the first input of the unit of the counter counter and through the second element, the second input of which is connected to the output delay - to the information inputs at the generator uniformly second and second keys, the outputs of which are co-distributed random numbers, the output unified with clock inputs 5 Less comparison block connected to respectively, the first and second accumulation input of the resolution of the account of the second counter, adders, the output of the first nakap-input of the installation in which is connected to beer adder is connected to the first output of the first delay element, the output of the adder, the second input of which is the overflow of the first counter is connected with the output of the second accumulating 10 keys to the second input of the OR element, an adder connected to the input of the dividend-output of which is connected to the inputs of the initial division block, the input of the divider of which is the installation of accumulating adders connected to the output of the adder, and exit with the input of the register synchronization.