SU985954A1 - Device for simulating distortions of telegraphy signals - Google Patents

Description

(54) DEVICE FOR IMITATION OF DISTORTIONS OF TELEGRAPH SIGNALS

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The invention relates to radio engineering and telecommunications and can be used to simulate distortion of telegraphic signals.

It is known a device for simulating binary signal distortions, containing a delay line, the main outputs of which are connected to the inputs of the first tator, the outputs are connected to the inputs of the first AND-NES element, the second switch, the output of which is connected to the first SX.OPIOM of the second element AND-NOT , third and fourth ILE elements, OR element, OR-NOT element, frequency divider and modulo two G1 adder

However, the known device has a low accuracy of imitation of distortion, which limits its scope.

The purpose of the invention is to improve the accuracy of imitation.

For this purpose, the third and fourth switches, two triggers and the element NOT, the output are introduced into the device to simulate the distortion of telegraph signals.

which is connected to the first input of the first Tripur, the second qusk of which is connected to the output of the OR element, whose inputs are connected to the third

. switch, the inputs of which are connected to the frequency divider codes, the clock input of which is connected to the first input of the back ground line, the second input of which is connected to the first output of the fourth switch, the second output of which is connected to the first input of the adder modulo two, the output of which is connected with the fourth input of the fourth xsallutator, the WPO of which input is connected to the first input of the third element and the second output of the second trigger, the second output of which is connected to the first input of the fourth element AND –NE, the second input of which a second n Vhods

Claims (1)

. the third, the output of the NAND and the additional output of the delay line, the third input of which is connected to the first input of the second switch, the second input of which is connected to the output of the first element, the inputs of which are connected to the inputs of the element OR NOT, the output of which is SOUTH connection to the third inputs The second switch, the output of which is connected to the input element NOT, the outputs of the third and fourth elements AND-NOT are connected respectively to the second and third inputs of the second element AND-NOT, the output of which is connected to the input of the second trigger, the output of the first three the gamer is connected to the third input of the fourth switch, the first input of the second switch, the third input of the third NAND unit, the third input of the fourth NAND unit and the fourth input of the fourth switch are the first second, third and fourth control inputs of the device, the clock and information inputs of which are, respectively, the clock input of the dantile frequency and the second input of the modulo two. The drawing shows a structural electrical circuit of the proposed device. The device contains the elements AND-NOT 1-4, the element OR-NOT 5, the element OR 6, the element NOT 7, the triggers 8 and 9, the divider 10 frequency, the adder 11 modulo two, line, 12 delays, switches 13-16. The device works as follows. The imitation of the distortion type of fragmentation is set by applying to the fourth control input of the device (the fourth input of the switch 15) the voltage of the logical unit. In this case, the switch 15 switches the third input with its first to the second outputs, and its first input with the third output (device output). The clock input of the device from the external master rerierator receives a continuous sequence of high-frequency clock pulses, and the information input. device (the second input of the adder 11 modulo two) is the input square signal, which should be subjected to distortion type crushing. The sequence of input frequency-frequency pulses is subjected to division in the 1O divider frequency. By setting the switch 16 to the desired position, a selection is made of the repetition period of distortions such as splitting the input telegraph signal. Setting a constant repetition period of crushing is done by committing only one of the inputs of the element OR 6 with the output of a certain bit of the frequency divider 10. To set a variable (for example, close to randomly varying) period of crushing following, switch 16 commutes a few (the more, the closer the approximation to a random law. Distribution) input element OR 6 with certain (not multiple of division ratio) outputs of frequency divider 10 . The formation of the signal at the output of the element OR 6 leads to the installation of the trigger 9 in the unit state, the signal from the output of which through the switch 15 is fed to the second Sysod line 12 of the delay and to the first input of the adder 11 modulo two. A delay line 12 is triggered, as a result of which pulses are generated at its main outputs. If it is necessary to form constant crushing durations, a logical zero level is present at the first control input of the device, as a result of which the switch 14 switches its output to its second input, while due to the absence of a signal at the third input of delay line 12 each The arrival of the signal at the control input of the delay line 12 leads to the formation at its main outputs of the same (i.e., each time repeating) sequence of pulses. Through the switch 13, which commutes certain main outputs of the delay line 12, the required magnitude of the crushing duration is established with the inputs of the AND-NO element 4 (e.g., as a percentage of the elementary telegraph cable duration). The signals from the OCHOI outputs of the delay line 12 go through the switch 13 to the inputs of the NAND 4 element with a time shift relative to the front edge of the signal at the second input of the LINE 12 delay. If there are signals at all inputs of the NAND 4 element, a logical zero voltage signal is generated at its output, which through the switch 14 and the NOT element 7 resets the trigger 9 to the zero state, as a result of which the support line 12 is reset. Due to the fact that the signal from the output of the trigger 9 through the switch 15 acts on the first input of the adder 11 modulo two, then at the output of the adder And modulo two, as well as at the output of the device, a telegraphic i signal is generated that is analogously received at the second input of the adder 11 modulo two, but subjected to crushing, the duration of which is equal to the time the trigger 9 is in a single state. If it is necessary to form variable over the duration of the crushing, the voltage level at the control input input of the device therefore, the switch 14 commutes its output with its third input, and because of the presence of a voltage of a logical unit at the third input of delay line 12, each arrival of a signal at the second input of delay line 12 leads to the formation of outputs of different (i.e., coming from each new point of reference) pulse sequences. By means of the switch 13, which switches certain outputs (not multiples of the division factor) delay lines 12 with the inputs of the element OR NOT 5, the required character of the change and the value of the crushing are established. The formation of the first pulse at any of the inputs of the element OR NOT 5. results in the formation of a voltage zero signal at its output, which the switch 14 and the element NOT 7 reset the trigger 9 to the zero state, which stops the formation of pulses: the outputs of delay line 12, although not bringing it back to its original state. The output signal of the trigger 9 is summed modulo two with the input telegraph signal, as a result of which the formation of telegraph sigals subjected to fragmentation of variable duration is output. It follows that when forming a scientific research institute distortions such as crushing, the elements NE-1-3 and trigger 8 do not affect the operation of the device, since the second input of the switch 15 is closed at this time. . Imitation of all other types of distortions, except for crushing, is provided by applying a logical zero to the fourth control input of the device. In this case, the switch 15 switches its first code with the first input, and the second and third outputs - with the second input. In this case, the element OR 6, the element NOT 7, the trigger 9, the frequency divider U and the switch 16 do not affect the operation of the device, since the third input of the switch 15 is closed. For HMiiTauHH postadapted by the great prevalence and single shifts of the transmitted information, the first control input of the device is supplied with a logic zero voltage, as a result of which the switch 14 switches its output with its second input. A one-time shift of the transmitted message elements is accomplished by applying a logic zero to the second and third control inputs of the device. in the initial state on the first output of the trigger 8 there is a voltage of logical zero, and on its second output a voltage of logical one. Upon arrival at the information input of the device of a rectangular telegraph signal at the output of the adder 11 modulo two, a voltage level of a logical unit is formed, on the leading edge of which a delay line 12 is triggered, as a result of which a short single impulse is generated at its additional output (which does not influence the operation of the device, since the elements AND-NOT 1 and 2 are closed), and at the main outputs there is formed 5 a sequence of mvshylc6v. By means of the switch 13, the required amount of shift is established (e.g., as a percentage of the duration of the elementary telegraph signal). The signals from the main outputs of the delay line 12 arrive through the switch, 13 to the inputs AND-NOT 4 with a shift in time relative to the front edge of the signal at the second input of the delay line 12. If there are signals at all inputs of the NAND 4 element, a voltage level signal of logical zero is generated at its input, as a result of which an output of the NAND 3 element generates a pulse that translates the trigger 8 into a new stable state. In this case, at the second output of the trigger 8, a logic zero level is set, and at the first output, a single voltage level is set. Thus, at the output of the device, the output pulse is formed after a time t from the arrival of a telegraph signal at the input of the device. Along with this, the arrival of a unit voltage level at the first input of the adder 11 modulo two leads to the formation of a zero voltage level at its output, setting the delay line 12 to its initial state. Further, the state of all elements of the device remains unchanged until the end of the input telegraph signal. At the moment of termination of the input signal, a single voltage level is generated at the output of the adder 11 but module two, again starting the delay line 12, as a result of which, at the output of the NAND-4 element, a short voltage pulse of logical zero is generated and switches (through commutator 14 and the element AND-NOT 3) triptvr 8 to a new stable state. In this case, a voltage level of zero is formed on the device code, and the zero signal from the code of the adder 11 modulo two sets the delay line 12 to its original state. Thus, in the device code, a signal was formed that is equal in duration to the telegraph signal received at the device input, 10 delayed relative to it in time by the value of t. Further, the state of all elements of the device remains unchanged until the new telegraph signal arrives at the information input of the device. Simulation of the current-free distortion type (i.e., shortening of the beginning of the telegraph signal by the value of t) is carried out by applying the voltage of a logic unit to the second control input of the device. In this case, in the initial state at the third input of the element AND-NOT 1 there is a unitary voltage level, and at its first input - the 31st level. Therefore, the formation of a short pulse at the additional output of the delay 12 at the time of the appearance of the telegraph signal at the information input of the device will not result in the output of the AND-NE element 1, and the value of 11T, at the output of the device, is the leading front of the output signal will appear to be delayed relative to the input to the vesh t. However, after switching the trigger 8, the same and ibie signals are present on the first and third inputs of the NAND 1 element. For this reason, at the moment when the input telegraph signal ends at the information input of the device, a short pulse generated by starting line 12 of the delay w or additional output will pass through the AND-NE 1 element to the IN-3 element input, as a result, the trigger 8 will switch to the new initial state At the same time, at the output of the device, a zero signal is formed, which returns the delay to the initial state. Thus, at the output of the device, a signal is generated that has a distortion of the type of shortening the beginning of the input telegraph signal by the value of t. Simulating current distortion of the type of current prevalence (i.e., extending the end of the signal by the value of t) is performed by applying a logical voltage to the third control input of the voltage device. units. In this case, at the moment when the input telegraph signal arrives, the AND-NOT 2 element will work, the signal from the output of which will trigger the trigger 8 to a new stable state, a single signal from the output will pass to the output of the device and will prevent the input telegraph signal from passing through the adder 11 module two, the zero signal from the output of which will set lily 12 delay to the initial state. Thus, a signal is generated at the output of the device, the beginning of which coincides in time with the input signals (1 telegraph signal. At the time the input telegraph signal ends, the single signal starts the delay line 12 again. However, the short pulse that forms at its additional output does not pass through the element AND-NOT 2, close the input signal with a zero signal from the second output of trigger 8. Therefore, the triggering of trigger 8 will occur only after the time –fc (set, as in the case of simulated information shift, the switch by means of a signal from the output of the element NE-NE 4. Thus, a signal is generated on the output of the device that has a distortion such as extending the end of the input telegraph signal by the value of t. In the case of applying a voltage of logical unit to the second and third control inputs of the input telegraph The signal passes to the output of the device without change. Simulation of variable dominance and edge distortion (variable telegraph shifts) is carried out in the same way as simulated TosoDJbix of dominance and shift information. However, instead of the zero voltage level, a single level is applied to the first control input of the device, as a result of which the switch 14 switches its output to its third input, and the delay line 12 is switched to the mode in which each input signal to its second input leads to the formation at its main outputs of pulses with different (i.e., coming from different time points of reference) rdvig. The nature of the changes and the magnitude of the shifts t is established by commutator cm 13 by analogy with the case of the formation of variables according to long-term crushing. Thus, the proposed device possesses much more VLBSHI functionality, the check is known, since it allows, besides its functions, to simulate variable in frequency and duration of laziness & laziness, variable in magnitude current and unavoidable prevalence, variable edge distortion and information shifts (transition swings, characteristic distortions, etc.), i.e. provides higher accuracy of imitation of distortion. The invention is a device for simulating telegraph signal distortion, containing a deceleration line, the main outputs of which are connected to the inputs of the first switch, the outputs of which are connected to the inputs of the first AND – NE element, the second switch, the output of which is connected to the first input of the second element AND NOT, the third and fourth elements AND-NOT, the element OR, the element OR-NOT, a frequency divider and a modulo-two adder, characterized in that, in order to vary the accuracy of the simulation, the third and fourth switches, two triggers and elements are introduced into it The ent is NOT, the output of which is connected to the nepBbtM input of the first trigger; the second input of which is connected to the output of the OR element, whose inputs are connected to the outputs of the third switch, whose inputs are connected to the outputs of the frequency divider, the clock & stroke of which is connected to the first input of the 96-pin 4 line, the second input of which is connected to the first output of the fourth switch, the second output of which is connected to the input of the adder. modulo two, the output of which is connected to the first input of the fourth switch, the second input of which is connected to the first input I will give the third element NAND and the first terminal of the second trigger, the second input of which is connected to the first input of the fourth element I-4 {E, the second input of which is connected to the second input of the third AND element and NOT to the additional delay line, the third the input of which is connected to the first input of the second switch, the second input of which is connected to the output of the first NAND element, whose inputs are connected to the inputs of the OR-NOT element, the output of which is connected to the third input of the second switch, the output of which is connected to the input of the HE element, O Odes of the third and fourth elements AND-NOT are connected respectively to the second and third inputs of the second element AND-NOT, the output of which is connected to the input of the second trigger, the output of the first trigger is connected to the third input of the fourth commutator, the first input of the second switch. The third NAND element, the third input of the fourth element and the fourth input of the fourth switch are respectively the first, second, third and fourth control inputs of the device, the clock and information inputs of which are are, respectively, the clock input of the frequency divider and a second input of the adder of modulo two. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 491219, cl. H 04 L 3 / O2, 1973 (prototype). 1c f f fJ