SU786034A1 - Discrete synchronization device - Google Patents

Description

one

The invention relates to a communication technique, in particular, to a technique for transmitting discrete data and can be used in automatic frequency control devices to ensure synchronous operation in systems for transmitting and receiving discrete information.

A discrete synchronization device is known, comprising a edge extraction unit and a serially connected master oscillator, a control unit and a controllable divider ij.

 However, such a device has a small frequency band of synchronization and does not ensure that the synchronization condition is met when receiving signals of a high duty cycle.

- The purpose of the invention is to expand the frequency range.

To do this, a discrete synchronization device containing a frontalization block and a serially connected master oscillator, a control unit, a controlled divider, a delay register, a memory register, an adder, and OR, AND, OR, NOT, switch and decoder elements are entered, whose output through the serially connected delay register, AND and OR-NOT elements are connected to another input of the control unit. The output of the edge selection block is connected to the first input of the memory register and, accordingly, through the switch and via the OR element to the corresponding inputs of the controlled divider, the output of which is connected to the inputs of the deshifter. Memory register outputs connected

10 to the inputs of the adder, the first output of which is connected to another input of the AND element, and the second outputs to the second inputs of the memory register, the third input of which is connected to the second home of the OR-NOT element, another input of the OR element and another output of the delay register, the second input which is connected to the output of the master oscillator and the input of the edge selection block, the output of which is connected to

the third input element OR NOT. Other inputs of the adder and switch combined.

The drawing shows the functional $ 2 on the electrical circuit of the proposed device ..

The device contains a block of fronts 1, a master oscillator 2, a control block 3, a controlled divider 4, a delay register 5, a register

Memory b, adder 7, elements OR, AND and H7IH-HE, 8, 9, and 10, switch 11 and decoder 12.

The device works as follows.

On the input buses, the binary code of the clock sequence of the input information is set. The bits 1 ... It is connected to the same inputs B of the adder 7, the remaining bits through the same inputs of the switch 11 with the subsequent inversion are connected to the information inputs of the divider 4, and through the inputs B of the switch 11 the same bits are connected with a shift by one bit d in the direction of the younger.

The input signal from the receiver output enters the selection fronto block in

I, where the information is tied to the frequency of the oscillator 2, In the selection unit of the fronts 1, pulses of duration equal to the period of the pulses of the oscillator 2 and corresponding to the front and rear edges of the received signal are formed. Each pulse from the edge selection unit 1 is fed to the input V of the switch 11 and, for the duration of the action, switches the value of the set code on the tires (k. + 1). . .h. At the same time, the output of the switch 11 is set to the inverse code of the half value of the period of the clock sequence of input information. The same pulse resets memory register b to zero and, through the element OR 8, writes to divider 4 set at the switch output

II, code. At the same time, the same pulse through the element OR-NOT 10 is supplied to the control unit 3, where the exclusion of a single pulse of the generator 2 at the input of the divider 4 is performed. Thus, the divider 4 sets a code equal to the difference of the capacitance of the divider 4 and the inverse code of the half period value. Next, the number of incoming reference pulses is counted, and when a 4 code value is reached in the divider equal to 11 ... 101 on decoder 12, a pulse is generated, which from the output of decoder 12 enters the input of delay register 5. Shift of delay register 5 is produced by pulses of generator 2. From output . the first bit of register 5 is transmitted to the output of the device, this pulse is spread out in time almost in the middle of the elementary parcel of the received information, i.e. the frequency is adjusted immediately in the first period. This front edge overwrites the value of the code of adder 7 into memory register b, the outputs of which are connected to the same inputs of adder 7. At the output of adder 7, the result of adding the remainder connected to inputs b and the value written in memory register b. Memory register b is executed on D-triggers. The same impulse goes to the element OR 8, i.e. a similar recording is made to the divider 4 of the code set at the output of the switch 11, but already corresponding to the period of the clock sequence in the discrete clock of the generator 2. The same pulse arrives at the OR-NOT 10 element, i.e., excluding one pulse of the generator 2 at the input of the divider 4. The pulse from the last bit of the register of delay 5 does not pass through the element AND 9, which is closed by a low potential from the transfer output of the adder 7. Since during the operation of the divider 4, the pulses are eliminated at its input X11 The 1m output pulse and the output pulse are additionally delayed by one discrete oscillator 2, the decoder 12 is assembled by the number 11 ... 101 and made using the matching cell on (k + 1)

inputs.

Subsequent pulses on the device output appear ahead of the actual value by the residual value and this error increases with each period and when it reaches or exceeds the generator 2 discrete value, the transfer signal from the last digit of the register will arrive at or exceed the generator 2 value. 5 delays through an AND 9 element on an OR-NOT 10 element. As a result, one pulse of the generator 2 at the input of the divider 4 is eliminated. At the same time, the output phase pulses are in phase. The resolving potential from the transfer output is held until a pulse appears at the output of the device, which rewrites the code value at the output of adder 7 as the remainder D in memory register b, and at the output of adder 7 thereafter, the sum L-fc + D-b is removed and removed transfer signal. The next exclusion of the pulse at the input of the divider 4 will occur when the new amount exceeds the discrete value of the generator 2. The delay of the pulses relative to the output pulses is selected based on the speed of operation of the adder 7 and the memory register 6.

Claims (1)

Thus, when using the proposed device, after the initial setup, the pulses at the output of the device are shifted in the direction of advance relative to the actual value of the period of the clock sequence by no more than the sampling of the master oscillator. This makes it possible to extend the range of operating frequencies. In addition, the device operates with input signals that have a high duty cycle and different values of the clock sequence period, both multiples and non-marginal periods of the master oscillator within the capacity of the controlled divider. The wide frequency range of synchronization and the simplicity in managing the reorganization of the repetition period of the output pulses, achieved by introducing new blocks and elements, expands the field of application of the device and eliminates the need to develop a number of such devices for each input frequency frequency. A discrete synchronization device comprising a photofactenter and a serially connected master oscillator, a control unit controlled by a divider, characterized in that, in order to expand the frequency range, a delay register, a memory register, a matrix, and OR elements are entered. , AND, OR-NOT, the switch and the decoder, the output of which is connected through another serially connected delay register, the element AND and ORINE is connected to another input of the control unit, and the output of the edge selection block is connected to the first input register memory and, respectively, through the switch and through the OR element to the corresponding inputs of the controlled divider, the output of which is connected to the inputs of the decoder, and the outputs of the memory register are connected to the inputs of the adder, the first output of which is connected to another input of the AND element, and the second outputs - to the second the inputs of the memory register, the third input of which is connected to the second input of the element. OR — NO, another input of the element OR and another output of the delay register, the second input of which is connected to the output of the master oscillator and the input of the block and fronts, which is connected to the third input of OR-NO element, wherein the other inputs of the adder and switch combined. Sources of information taken into account in the examination 1. USSR author's certificate 314320, cl. H 0.4 L 7/02, 30.03.70 (prototype).