SU843284A1 - Device for receiving address signals into asynchrono-pulse communication systems - Google Patents

Description

(54) DEVICE FOR RECEPTION OF ADDRESS SIGNALS IN ASYNCHRONOUS-PULSE COMMUNICATION SYSTEMS

one

The invention relates to telecommunications and can be used for noise-resistant allocation of address signals in asynchronous-pulse communication systems.

Devices are known for receiving address signals in asynchronous-pulse communication systems containing a shift register connected via a decoder to the keys included at the input of the receivers of communications 1.

The closest technical solution to the present invention is a device for receiving address signals in asynchronous-pulse communication systems comprising a pulse reception unit, a shift register, a logic unit, a decoder, the corresponding inputs of which are connected to the inputs of the threshold unit, keys whose outputs are connected to inputs of receivers of information, the corresponding inputs of keys. are connected to the first output of the receiving unit of pulse signals, the corresponding outputs of the decoder are connected to the corresponding inputs of the cell Yuchey 2.

However, the known devices have low noise immunity.

The purpose of the invention is to increase noise immunity.

To do this, the device for receiving address signals in asynchronous-pulse communication systems contains a block for receiving pulse signals, a shift register, a logic block, a decoder, the corresponding inputs of which are connected to the inputs of the threshold block, keys whose outputs are connected to the inputs of information receivers corresponding the key inputs are connected to the first input of the pulse signal receiving unit, the corresponding outputs of the decoder are connected to the corresponding key inputs, a buffer shift register is entered, two blocks of the element And, the control unit, the switch and the memory unit, the outputs of which are connected to the corresponding inputs of keys, the inputs of the memory unit are connected to the corresponding outputs of the decoder and the corresponding inputs of the logic unit, the first output of which is connected to the first input of the first block of elements And, the second output logic block is connected to the first input of the second block of elements And whose outputs are connected

to the corresponding inputs of the switch, the outputs of the first block of elements And are connected to the corresponding inputs of the switch, the outputs of which are connected to the corresponding inputs of the descrambler, the first output of the buffer register is connected to the input of the shift register, the second, third and fourth outputs of the buffer register are connected to the corresponding inputs of the first block of elements And , the outputs of the shift register are connected to the corresponding inputs of the second block of elements AND, in addition, the first output of the control block is connected to the corresponding input the logic unit, the second output of the control unit is connected to the corresponding input of the memory unit, the third output of the control unit is connected to the corresponding input of the switch, the output of the threshold unit is connected to the first input of the control unit, the second and third inputs of the control unit are connected to the corresponding inputs of the logic unit, the corresponding the outputs of the second block of elements And connected to the corresponding inputs of the first block of elements I.

The drawing shows a diagram of the proposed device.

A device for receiving address signals in asynchronous-pulse communication systems comprises a pulsed signal receiving unit 1, a shift register 2, a shift buffer register 3, the first block of 4 And elements, a second block of 5 And elements, a switch 6, decipher 7, a memory block 8 , logic unit 9, control unit 10, threshold unit 11, keys 12 and information receivers 13.

The device works as follows.

From block 1, the address codes of messages that arrive at arbitrary points in time are accumulated in the main n-bit shift register 2 and in the buffer (n-1) -discharge shift register 3.

Initially, the decoding of the address codes is performed from the main shift register 2 through block 4, connected by switch 6 to decipheror 7, with the selected addresses memorized in block 8.

Logic block 9 provides the exclusion codes allocated addresses from further analysis on block 4.

The remaining single signals and accumulated in the buffer register 3 shifts are connected by the switch 6 with different phase shifts 1.2 ... (n-1) in n bits in series to the decryptor 7, memorize the subsequent allocated address codes in block 8 and eliminate them with logical block 9 and block 5. If, as a result of the sequence of such actions specified by block 10, the number of remaining single signals. Since switch b will be a small amount not exceeding the specified threshold in block 11, then with a certain degree of confidence it can be assumed that these signals are due to the presence of channel impulses, and the allocation of addresses is correct. Then block 10 reads the stored addresses from block 8 and performs the corresponding switching of keys 12 at the input of receivers 13.

Otherwise (when the threshold values are exceeded in block 11), which is typical of the situation of allocating a false address, block 10 uses logical block 9 and block 4 to try to extract address codes in another combination with repeating the above steps to obtain a positive result. .

Thus, block 10 determines the priority and order of testing a combination of addresses and decides on the correctly received ones.

As a result, the impulse noise of the communication channel in combination with the received impulses of the subsequent addresses in most cases will not be able to receive the false address code of the message, which increases the noise immunity of the receiver.

At the same time, in order to maintain high speed, the device’s clock frequency may exceed the channel frequency of the received signals.

The proposed device allows improving noise immunity due to the possibility of correct allocation of addresses in the presence of a false set of the address code caused by a combination of impulse noise of the communication channel and the address codes of other messages.

Claims (2)

1.Agadzhanov I.A., Gorshkov VM, Smirnov G.D. Fundamentals of radio telemetry. Moscow, USSR Ministry of Defense, 1971, p. 148-154, p. 5-4. 2. USSR author's certificate According to application number 2675770 / 18-09, cl. H 04 L25 / 30, 1978 (prototype).