RU1802402C - Device for formation of digital signals - Google Patents

Abstract

The invention can be used in digital transmission systems. The device contains: 4 triggers (1, 2, 10, 14), 2 time delay blocks (7, 15), 2 switching blocks (11. 17), 1 OR-NOT element (8), 1 OR element (9), 1 element EXCLUSIVE OR AND (12), 1 inverter (13), 1 element AND (16), 2 clock buses (3, 5), 2 control buses (4, 6), 1 output bus (18) with corresponding functional connection mi. 5 ill.

Description

The invention relates to telecommunication technology and can be used in digital transmission systems.

The purpose of the invention is to expand the functionality of the device by generating not only a relative bi-pulse signal, but also RZ, BI-LNRZ-S, BI-M, DBI and MILLER signals.

Fig. 1 is a structural electrical diagram of a digital signal generating apparatus; Fig. 2 is a timing chart for generating a relative bi-pulse signal; Fig. 3 is a timing chart for generating signals RZ and NRZ-S; Fig. 4 is a timing chart for generating signals BI-L and Miller; Fig. 5 is a timing chart for generating DBI and BI-M signals.

The device for generating digital signals contains the first 1 and second 2 flip-flops, the first clock bus 3, the first control bus 4, the second clock bus 5, the second control bus 6, the first time delay unit 7, OR-NOT element 8, OR element 9 , third 10 trigger, first 11 switching unit, element 12 EXCLUSIVE OR. inverter 13, fourth trigger 14, second 15 time delay unit, element 16 AND, second 17 switching unit and output bus 18.

The first time delay block is designed to temporarily delay the clock signal supplied to the counting input of the first trigger, in order to ensure that the edges of the clock signal coincide in time with the digital signal supplied to the enable input of the first trigger, which is necessary to generate all signals except the relative bi-pulse one. The time delay can be carried out, for example, using an integrating circuit with an appropriate selection of its parameters.

A second block of time delay can be constructed similarly, which delays the signal by a time equal to T / 2 (T is the clock interval).

The first and second switching units contain sets of mechanical or electronic keys, by which the generated signal is selected.

The remaining units are standard telecommunication units.

A device for generating digital signals operates as follows.

An initial digital signal of the NRZ-L type is supplied to the enable input of the first 1 trigger, which must be converted into one of the following signals: relative bi-pulse, RZ, BI-L, NRZ-S, BI-M, DBI, and MILLER.

A relative bi-pulse signal is generated using triggers 1 and 2 and

element 12 EXCLUSIVE OR.

The digital signal NRZ-L (figa) from the first control bus 4 is fed to the enable input of the first trigger 1, the counting input of which receives a signal from

0 of the first clock bus 3 (figb). The first trigger 1 switches due to the transition from a low to a high signal from the first clock bus (Fig. 2b); if the information signal from the first control bus 5 (Fig. 2a) is high at its enable input. Otherwise, the first trigger 1 does not switch. Similarly, the second trigger 1 switches under the influence of the transition from low

0

level in a high signal with a second clock

bus 5, inverse with respect to the first clock bus 3 (Fig. 2d), supplied to its synchronizing input, if the clock signal (Fig. 2c), supplied to its resolution input from the second control bus 6, is at a high level. Otherwise case switching does not occur.

The output signals of the first 1 and second 2 flip-flops (fig.2d, e) are fed to the fourth and fifth inputs of the first 11 switching unit, in which the corresponding switching is preliminarily performed so that the signals from the second and second outputs are switched accordingly and third entrances. Thus, the output signals of triggers 1 and 2 are fed to the inputs of element 1.2 EXCLUSIVE OR, where they are summed modulo 2. The output signal of this element

0 (Fig. 2l) is a relative bi-pulse signal in which in the middle of each clock interval there is necessarily a transition from one level to another, except for those clock intervals5 in which the signal is transmitted from the second control bus 6. At the borders the clock intervals the transition from one level to another is in the presence of 1 from the first control bus 4 (figa) and is absent

0 in the presence of O,

The output signal of the EXCLUSIVE OR element is supplied to the second input of the second 17 switching unit, which is preliminarily prepared for switching the signal from this input to the output of the device.

The RZ signal (Fig. 3P) is generated from the NRZ-L signal by halving the duration of the current transmissions. This operation is performed by element 16 I. The first input of which is supplied with the NRZ-L signal (Fig. 3a), and the second signal of the clock frequency (Fig. 3g) from the output of the first 7 time delay unit. The signal RZ received at the output of the element AND is switched to the output of the device from the sixth input of the second 17 switching unit.

The algorithm for generating the NRZ-L signal (Fig. 3c) is as follows: the symbol 1 of the original NRZ-L signal (fig. Za) corresponds to the repetition of the previous signal element, and the symbol O corresponds to the appearance of an alternative signal. The NRZ-L signal is generated using elements 8, 9, 10, and 11. The inputs NRZ-L (Fig. 3a) and a clock signal (Fig. 3j) are supplied to the inputs of the IL element AND NOT. At the output of element 8, the signal shown in Fig. 3c is generated, which is fed to one of the inputs of OR element 9. A signal NRZ-L is supplied to the second input of the OR element. The output signal of element 9 (Fig. Zi) is supplied to the counting input of the T-flip-flop 10, at the output of which an NRZ-S signal is generated (Fig. Zc). This signal is switched to the output of the device from the sixth input of the second 17, the switching unit.

The BI-L signal generating algorithm (Fig. 4m) is as follows: the symbols 1 and O in the original NRZ-L signal (Fig. 4a) are represented by symbol blocks 01 and 10, respectively.

To generate the BI-L signal to the inputs of the EXCLUSIVE OR element 12, the NRZ-L signal (Fig. 4a) and the clock signal from the output of the time delay unit 7 are switched from the first and second inputs of the first 11 switching units (Fig. 4g).

These signals are added modulo 2 (Fig. 4l). Further, the signal obtained as a result of the summation is inverted in the inverter 13, at the output of which a BI-L signal is generated (Fig. 4m). This signal is fed to the third input of the second 17 switching unit, from where it is switched to the output of the latter.

The MILLER signal generation algorithm consists in the following: the symbols of the initial sequence are encoded alternately high and low levels at clock intervals, and symbols 1 by blocks 10 and 01, but so that the first symbol of the block coincides with the previous symbol. This algorithm is implemented using a counting trigger 14, to the counting input of which a BI-L signal is supplied (Fig. 4m). The MILLER signal generated at the output of this trigger (Fig. 4o) is fed to the fifth input of the second 17 switching unit, from where it is switched to the output of the device. Thus, to generate the MILLER code

You must first receive the BI-L code.

The rule for generating the DV1 code is that both the symbol 1 of the initial sequence and the symbol O are encoded in blocks 01 or 10. In this case, the symbol 1 of the initial sequence corresponds to the absence of the transition of block 01 (or 10) to an alternative state (the block of the previous state is repeated nor), and the symbol O corresponds to a transition (a block is formed that is different from the previous one).

To generate the DV1 signal, NRZ-S signals obtained at the output of block 10 (Fig. 3K) and a clock signal generated at the output of block 7 are used. The DV1 code is generated as follows.

The signal NRZ-S (Fig.5k) is supplied to the fourth input of the first 1.1 switching unit, the fifth input of which receives a clock signal (Fig.5g) from the output of unit 7. These signals are switched to the outputs of the switching unit and fed to the inputs of element 12 EXCLUSIVE OR. At the output of element 12, a signal DV1 is generated (Fig. 5l), which from the second input of the second 17 switching unit is switched to the output of the device.

The BI-M signal differs from the DV1 signal only by a shift of half the clock interval. This delay occurs in the second 15 time delay block. Signal DV1 is fed to the input of block 15 (Fig. 5l), and a BI-M signal is generated at the output, which, through the fourth input of the second 17 switching unit, is output to the device.

Claims (1)

Claims A device for generating digital signals, comprising a first trigger, the synchronizing input of which is connected to the first clock bus, an enable input - to the first control bus, a second trigger, the synchronizing input of which is connected to the second clock bus, allowing the input - to the second control bus, element EXCLUSIVE OR and an output bus, characterized in that, in order to expand the functionality by forming not only a relative bi-pulse signal, but also RZ, BI-L, NRZ-S signals. BI-M, DV-1 and MILLER, the third and fourth triggers, the inverter, the first and second switching units, the OR-NOT element, the OR element, the AND element, the first and second delay blocks, the first input of the OR-NOT element, is introduced into it connected to the first input of an OR element with the first the input of the And element, with the first input of the first switching unit and with the first control bus, the second input - with the second input of the switching unit, with the second input of the And element and through the first delay unit with the first clock bus, the output - with the second input of the OR element, the output which is connected to the counting input of the third trigger, the output of which is connected to the first input of the second switching unit and to the third input of the first switching unit, the fourth input of which is connected to the output of the first and trigger, the fifth input - to the output of the second trigger, the first and second outputs, respectively, with the first and second inputs of the EXCLUSIVE OR element, the output of which is connected to the second input of the second switching unit, with the input of the second time delay unit and with the inverter input, the output of which is connected to the counting input of the fourth trigger and to the third input the second switching unit, the fourth input of which is connected to the output of the second time delay unit, the fifth input with the output of the fourth trigger, the sixth input with the output of the And element, the output with the output bus, P P -pppp -pppppppppp-g „P P P PPPPPP ..ppppppppg „P P P L G d P g FIG. / T TO. STD LPPPGGPPPPPPPPPG L PP P P PPPP PGT L PP P P PPPP PP FIG. S