SU985788A1 - Microprogram control device - Google Patents

Description

(5) MICROPROGRAM CONTROL DEVICE

The invention relates to a computational gel technique and can be used in the synthesis of devices for digital computers. A firmware control device is known that contains a memory block, two counters, two decoders, a micro-command register, a pulse generator, a group of (K + 1) AND blocks, and an OR block tl II. The disadvantage of this device is the low efficiency of the memory block, due to the fact that only an integer number of microinstructions can be stored in the memory block. The closest to the proposed technical essence and the achieved positive effect is a firmware control device containing a memory block, two counters, two decoders, a microinstruction register, two delay elements, 2E + im + 1 block of AND elements, a block of OR elements, a group of TP elements OR, an AND element, a one-shot, a trigger, a clock pulse generator 2. The disadvantage of this device is its low functionality, which is due to the inability to implement microprograms consisting of mic okomand, a width of which is greater than the length of lines of memory block, the remainder of the whole microinstruction should not exceed half the length of microinstruction format; the inability to control large-scale operating devices, i.e., operating devices for which a large number of control actions (microoperations) need to be formed in each operation cycle, in each cycle the device can issue microcommands whose total number of bits is less than the ruler length residues; the complexity of readout schemes, which leads to a reduction in overall fault tolerance and complicates the process of manufacturing such devices in the 3985 integral design; the complexity of modifying the scheme when changing the parameters of the micro-program. The purpose of the invention is to expand the functionality of the device. The goal is achieved by having a device containing a memory block, two counters, two decoders, a microcommand register, two delay elements, 2K + mf1 AND block (micro format, the number of full rulers microcommands in memory), block of elements OR, group of m elements OR,; element And, one-shot trigger, clock pulse generator, the information input of the first counter is connected to the input of the device’s initial address, and the output is connected to The main input of the first decoder, the output of which is connected to the address input of the memory block, the information output of which is connected to the first inputs 1 (C + 1) of blocks of elements I, the outputs of the register of microinstructions are connected to the first inputs (+2) - (2ё + 1) - And units of the blocks, outputs (2E + 2) - () of the blocks of elements And are connected to the inputs of the first block of elements OR whose outputs are connected to the output of the device microoperation, the single trigger input is connected to the device start input, the single output to the first input element And, the second input of which dinene with the output of the clock pulse generator, the output of the element I is connected via the first delay element to the counting input of the second counter, the output of which is connected to the input of the second decoder, the first output of which is connected to the second input of the (E + 1) -th block of elements AND, additionally a buffer register is entered, the setup input of the second counter is connected to the input of the device's initial address, 1 and the output () of the j-th group of outputs of the second decoder () are connected to the y input of the f-ro element OR of the group whose outputs are connected to the second inputs i -ro of the block of elements And, the output of which is connected to the register input of micro-commands Se, the outputs of the j-th group of outputs of the second decoder are connected respectively to the first inputs (2K + 2) - (2e + mf 1) -th blocks of elements And, the output of the 6th the element OR of the group is connected via a one-shot with the inverse input of the AND element, the output is connected to the control input of the memory unit and through the delay element to the counting input of the first counter, the output of the -th element of the OR group is connected through the delay element to the second inputs (B + 2) - (5P + -NGN-1) -th blocks of elements I; outputs (P + 2) - (2P + 1) -th blocks of elements And are connected to the output of the device microoperations; the output of the (P + 1) th block of the elements And is connected to the information input of the buffer register, the outputs of which are connected by the third inputs of the (2e + 2) - (2P + rm-1) th blocks of the elements I. The essence of the invention is to improve the efficiency of the memory block These control devices by recording individual microcommands of any format p of the memory ruler, including microcommands with a format larger than the size of the ruler, and residues of various lengths not included in these rulers, in separate cells. The drawing shows the functional diagram of the device / Device contains first estimator 1, first decoder 2, memory block 3, (1-P) -th block of AND units, register of 5 micro-commands, (+2) - () block of 6 AND elements, output 7 of device micro-operations, second counter 8 , second decoder 9 group of 10 elements OR, (e + 1) -th block of elements AND 11, buffer register 12, (22 + 2) - (26+ + Gp + 1) -th block of 13 elements AND, block 1 of elements OR , first delay element 15, second delay element 16, trigger 17, clock pulse generator 18, AND 19 element, one-shot 20, In the initial state, both counters 1 and 8 and trigger 17 are in the zero state, AND 19 is closed, region lines of microinstructions 5 and buffer 12 are free. The proposed device works as follows. At the starting address arriving at the first input of counter 1 and the input of counter 8, the first decoder 2 initiates the output corresponding to the starting address, and the second decoder 9 excites the zero output. The start trigger signal 17 is set to one state, allowing the passage of pulses from generator 18 through element 19. The first pulse enables reading of information from the initial cell of memory block 3. Through an open decoder 9 (6 + 1) -i block of elements And 11, this information is written into the buffer register 12. After the time determined by the delay element IS, the counter 8 is set to the state corresponding to one at the first output of the decoder 9- The second the pulse reads information from the next line of memory block 3 and through the open elements of the AND (1-P) -th blocks of the k elements of AND, is written into the first field of the register of 5 microcommands. After the time determined by the delay element 15, the counter 8 is set to the state to which the unit corresponds, at the second output of the decoder 9, and the counter 1 to the state according to which the next line of the memory block 3 is selected. Then, pulses from generator 18 read information from. memory block 3 and recording it in the corresponding fields of the register of 5 micro commands (2 + 1) -m pulse of the generator 18, information is stored from memory block 3 in the S-th register register 5 micro instructions. A single signal from the th output of the decoder 9 arrives at the first input of the (2e + 2) th block 13.1 of the element I. After the time determined by the delay element 16, all P fields of the microinstruction register will be filled and all the second inputs of all (E + 2 ) - (2 + m1N-1) blocks 6 and 13 of the elements I receive signals permitting the reading of information. Content (1-C) -th. the register fields of 5 microcommands and the first field of the buffer register 12 arrive at output 7 In addition, the signal from the output of the nd element OR of group 10 of the elements OR is fed to the input of the one-shot 20, which forms a signal of the desired duration and prevents the passage of pulses from the generator 18 through element AND 19, (+2) -th pulse in the circuit is not supplied. After the expiration of the time required for outputting information to output 7 and determined by the element 15. Delays, counters 1 and the B (6 + 1) -th pulse are transferred to the state corresponding to the units on those outputs of the decoders 2 and 9, by which information is read from the first ruler of the memory block of the group of rulers corresponding to the second microcommand. After the end of the pulse produced by the single vibrator, the clock pulses are again fed into the circuit through the open element I 19 and the first pulse is read by the first pulse following

microscopic commands. Next, the device works as described above.

When reading whole parts of the second micro-command Мз у,

2 1 21 M 25. . . Mjg

WM2 controls the signals from the second group of outputs of the decoder 9, and so on. After reading the mth microcommand, counter 1 records the address of the next group of microcommands either by natural addressing or by forcing the address code from the device input.

Claims (1)

1. Geolets A.G. Nairi-3 computer, M, Statistics, 1979, p. 132. The author's certificate of the USSR according to application number 29b1 311 / l8-2t, cl. G06F9 / 22, 1980. 8 commands, Ee outputs / -and groups of outputs of the second decoder are connected to the first inputs (2Е + 2) - (2С + гн-1) -th blocks of the And elements, output of the S-ro element OR of the group connected via a one-shot with an inverse input of the element I, the output of which is connected to the control input of the memory unit and through a delay element to the counting input of the first counter, the output of the f-th element of the OR group is connected through the delay element to the second inputs (+2) - (2e + PI-1) of the And blocks of the elements, the outputs (8 + 2) of the (28 + 1) th blocks of the And elements are connected to the output of the device microoperations, the output (8+ The 0th block of elements I is connected to the information input of the buffer register, the outputs of which are connected to the third inputs (22 + 2) .- (2c + n "-1) -th blocks of elements I. Of rf -07 4.1 a 5T7G P2t: I / fi 14 ItttH m im