SU970718A1 - Time mark forming device - Google Patents

Description

(3) TEMPORARY TIMER FORMER

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The invention relates to a paAHotexnik and can be used in radio communications and radio navigation.

Known timestamp driver containing serially connected frequency divider and matched filter 1 J ;.

The disadvantage of such a driver is a long time tagging time.

The purpose of the invention is to reduce the time it takes to form a time stamp.

This goal is achieved by introducing two decoders, a delay element, an OR element and a key, to the control input of which the output of the frequency divider is connected to the known input of the time stamp into a known timestamp generator containing a serially connected frequency divider and a matched filter. the filter whose output is connected to the inputs of the decoders,

the output of the first decoder through the delay element, and the output of the second decoder is directly connected to the inputs of the OR element.

FIG. Figure 1 shows the electrical layout of the driver; in fig. 2 - timing diagrams illustrating the work of the driver.

shaper timestamp contains frequency divider 1, key 2,

10 matched filter 3, decoders 4 and 5 delay element 6, element OR 7.

The device works as follows.

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The input of the key, 2, receives a signal from the input half-bits (Fig. 2 € |) from the output of the receiver, consisting of (par 1 and O. Each pair forms a code element

20 Barker, and element 1 corresponds to pair 10, to element O pair 01. The control input of key 2 receives a signal from the output of the frequency divider, which receives a synchronization signal with a frequency of half-bouncing from the output of the receiver. At the output of frequency divider 1, a frequency is formed two times lower than the input bit frequency. With the correct phasing of the frequency divider 1 (Fig. 26}, the output signal of the key 2 has the form (Fig. 2ti), and the response of the matched filter (SF) 3 working with a clock frequency of the bit from the frequency divider 1 has a positive sign (Fig. 21) If the frequency divider 1 is phased incorrectly (Fig. 2E), the signal at the output of the key 2 has characters inverted and shifted by the nibbled interval (Fig. 2e). The response of the SF 3 (Fig. 2g) has the opposite sign and is delayed by time L, equal to one polubits interval. This response, extracted and transformed by the second decoder 5, n steps as a time stamp through the element OR 7 at the output of the device. Positive response of the matched filter 3 corresponding to the correct phasing is extracted and transformed by the first decoder C, delayed by the half-bit in the delay element 6 and fed through the element OR 7 to the output of the mouth in the form of a pulse of a timestamp (Fig. 2a) Thus, in the former, there is no process of pre-phasing of the bit-frequency clock signal, which speeds up the time stamp to be obtained approximately twice, and also not buets bit allocation units and the wrong bit error counters and error interval as in the known device, which greatly simplifies the device. Claims of the invention: a timestamp driver containing a serially connected frequency divider and a matched filter, characterized in that, in order to reduce the timestamp time, two decoders, a delay element, an OR element, and a key, to the control input of which the output frequency divider are connected, are introduced and the output of the switch is connected to the input of the matched filter, the output of which is connected to the inputs of the decoders, while the output of the first decoder through the delay element, and the output of the second decoder directly Stately connected to the inputs of the element OR. Sources of information, p (1n t in consideration in the examination 1. US patent No. 3551814, CL 325 38, 1970 (prototype).

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Claims (1)

Claim A time stamp generator comprising a frequency divider connected in series and a matched filter, characterized in that, in order to reduce the time stamp formation time, two decoders are introduced, a delay element, an OR element, and a key, to the control input of which a divider.frequency output is connected, and the key output is connected to the input of the matched filter, the output of which is connected to the inputs of the decoders, while the output of the first decoder through the delay element, and the output of the second decoder is directly connected to moves the OR.