SU1275740A1 - Device for generating pulses with changing repetition frequency - Google Patents

Abstract

The invention can be used in the development of pulse generators with varying frequency. The purpose of the invention is to expand the functionality achieved by providing a linear and quadratic reduction of the output frequency as a function of time. The third, fourth and fifth controlled frequency dividers, the third and fourth counters, the third frequency divider with a constant division factor (CD) are entered into the device. The drawing shows controlled dividers 1-5 frequencies, counters 6-9, forming control codes, dividers 10-12 with a constant CD, reference frequency bus 13, preset bus 14. The outputs of the controlled frequency dividers are the outputs of the device. At the same time, at the first output a sequence of pulses is formed with a linearly increasing frequency, at the second with a linearly decreasing frequency, at the third - with a quadratically decreasing (L with a frequency. All indicated sequences can be formed simultaneously. 1 ill. IsD LED 4

Description

The invention relates to a pulse technique and can be exploded (developed in the development of pulse generators with varying frequency. The purpose of the invention is to expand the functional capabilities of the device by providing a linear and quadratic reduction of the output frequency as a function of time. The drawing shows the functional diagram of the device for generating pulses with varying frequency of the following. The device contains controlled frequency divider 1-5 frequencies (UDCH), counters 6-9, which form the control codes, de 10-12 frequencies with dividing ratios, frequency reference bus 13, transducer installation bus 14. UDCH counters 1-4 and frequency divider 11 are connected to reference frequency bus 13, UHF dividing factors setting inputs 1-4 are connected to the outputs of the rows of counters 6–9, respectively, the input of the installation of the UDCH 5 division factor 5 with the outputs of the bits of counter 4, and the installation inputs of the initial counters 6–9 with the bus 14 of the installation. The output of the UDCH 1 is connected to the counting input of the UDCH 5 - and the inputs of the forward counting of counters 7 and 8, the counting input of the counting 8 is connected to the output of the frequency divider 11. The input 10 of the frequency is connected to the output of the UDCH 2, and the output is connected to the counting input of counter 6. The input of the frequency divider 12 is connected to the output of the UDCH 3, and the output is connected to the input of the direct count of the counter 9. The outputs of the UDCH 1, 4 and 5 are respectively the first, second, and third outputs of the device. The device works in the following way. : In the initial state, the bus numbers 14 to the counters 6-9 are written to the numbers e (f then (f 90 respectively, determined from the conditions B 0 (1 NTO V "/ 2, (2) where F is the reference frequency of the pulses coming 1-gx bus 13; f the required initial frequency and rate of change of the frequency of the pulses at the first and third outputs of the device. 402 These numbers determine the initial division factors of the corresponding UDCH. The division factors of the dividers 10 and 12 are equal to 2, and the division factor of the 11 frequency divider is At receipt on the bus of 13 impulses with a frequency of FQ at the outputs of UDCH 1-5 forms pulses with frequencies determined by the numbers recorded in counters 6 to 9. Pulses from the output of UDCH 1 are fed to the input of the direct counting of counter 7, and pulses from the output of UDCH 2 through a divider 10 of frequency to the input of counting return of counter 6. Counter 7 operates in the forward counting mode and the counter in the counting mode 6. With each pulse at the inputs of counters 6 and 7, the control codes at the discharge outputs change by one. According to the change in control codeosis of counters 6 and 7, the division coefficients of UDF 1 and 2 also change, i.e. the division ratio of the UDCH 1 decreases; and the UDCH 2 increases, which leads to a change in the frequency of the pulses at the outputs of the UDCH 1 and 2, and the frequency of the pulses at the output of the UDCH 1 increases linearly. Indeed, to ensure the growth of the frequency of the pulses at the output of the UDCH 1 according to the linear law f, (t) f +, (3) where t is the current time; f, (t) is the frequency of the pulses at the output of the UDCH 1, the coefficient Hg (t) of the division of the UDCH 1 must change according to the hyperbolic law (ft) -2 f + uf-t. When f, (t) changes according to the law (3), the coefficient The N (t) division of the UDCH 2 varies according to the law t N, (t) I f (t) dt. Taking into account equations (2) and (3), we can write N (t) + + uf.tV2. The frequency f (t) of pulses at the input of counter 6, taking into account the division factor of the frequency divider 10, is determined as follows: FF s N: (t) 2 f 7if + 2ft + ft and f + t) 2- UHF 1 division factor constitutes

n. (t) N - rf "(t) dt l 60 -, 6

. dt

 Fa.

i Tf / d + t) f

about H f. fk / M Ei) t + f.and uf F а a The resulting equation coincides with equation (4). Consequently, the frequency f (t) increases in time according to a linear law (3). Pulses with frequency f (t) are fed to the direct counting input of the counter -8 to the counting input of which pulses are sent from the bus 13, passing through a pre-divider frequency 11. Taking into account the division factor of the frequency divider 11, the number of N-Ct) with counter 8, and hence the division coefficient of the UDCH 3, is determined as follows:. I fw (t) N (t) N + - 5 - fe-Kt. Taking into account equations (2) and (3), it is possible to write “3 (t) GI pulses from the output of the UDCH 3 through frequency dividers 12 are fed to the input of the direct count of counter 9. The frequency fAf (t) of the pulses at the input of the direct account counter. 9, taking into account the transmission coefficient, frequency divider 12 is defined as follows: t t f / "- l t-S 3 N. (t) 2 f; / Af-2f-t-H & f | (t -f: 7Zf The number Ng (t) in the counter 9, and consequently, the division coefficients of the UDCH 4 and 5 are. Ng (t) Ng + J fg (t) dt. Taking into account the equation 1n 1 (1) and ( 5) we can write down ZiL Л JJ1. F JV –Ь + (F) t - - H Af

or

N (0 .a.

Claims (1)

The UDCH 4 counting input has impulses of frequency FQ from the bus 13. The frequency f (t) of the pulses at the output of the UDCH 4, and consequently, also on the second output of the device (5) H) -5; T) F, / f - Af- t f - uf-t Ha countable input UDCH 5 impulses of frequency f. (t) from the output of UDCH 1. Frequency t; pulses at the output of the UDCH 5, and consequently, at the third output of the device f) Itiiaf .t) (-1 (0 fL FF o Thus, in accordance with equations (3), (6) and (7) at the first output devices form a sequence of pulses with a linearly increasing frequency, on the second with a linearly decreasing frequency, and on the third with a quadratically decreasing frequency, all of which specified sequences of pulses can be formed at the same time. Formula of the device for generating pulses with varying tracking frequency, The first and second controlled frequency dividers, the counting inputs of which are connected to the reference frequency bus, the first and second counters, the discharge outputs of which are connected to the installation inputs of the division factors of the corresponding controlled frequency dividers, the installation inputs of the initial states of the counters are connected to the installation bus, the output of the second controlled frequency divider is connected via the first frequency divider with a constant split factor connected to the countdown input of the first counter, BTOpofi a constant frequency divider the division factor, characterized in that, in order to expand the functionality, a third, fourth, fifth controllable frequency divider, third, fourth counters, a third frequency divider with a constant division factor, are introduced into it than the outputs of the bits of the third counter are connected to the input of the installation of the division factor of the third controlled frequency divider, the output of which is connected to the inputs of the division factors of the fourth and n through the third divider with the direct count input of the fourth counter; controlled frequency dividers, the output of the first controlled frequency divider is connected to the direct 75740. 6 the second and third counters and the counting input of the fifth controlled frequency divider, the counting input of the third counter through the second 5 frequency divider with a constant division factor is connected to the reference frequency bus, which is also associated with the third and fourth control inputs It is the clock divider, the bus is installed with the inputs of the installation of the initial states of the third and fourth counters.