SU968819A1 - Digital autocorrelator - Google Patents

Description

The invention relates to measuring the characteristics of random processes and is intended to determine the correlation function of the current stationary random process in real time.

A digital correlator is known that contains comparators, register, multipliers, integrators l1.

However, the analogue built on the principle of the sign correlator does not have high accuracy. The closest to the proposed device is a parallel action correlator containing an input memory block on Um cells, multiplicators, adders, two analog-digital converters, pulse generator . The first input of the device is. the first input of the first analog-to-digital converter (ADC), the output of which is connected in parallel to the first inputs of the multiplication units. To the second

. The inputs of the multiplication units are connected to the outputs of the corresponding cells of the input memory block. The second input of the device is sequentially connected to the first input (g) of the second ADC, the first input is the input to the foot of the memory unit, the second input of which is combined with the second inputs of the ADC and connected to the output of the pulse generator. The outputs of the multiplication units are connected through the corresponding adders to the corresponding outputs of the device.

A disadvantage of the known correlator is low speed.

15

The aim of the invention is to increase speed.

This goal is achieved by the fact that in a digital autocorrelator, containing. M multiplicators, the outputs of which are connected to the inputs of the corresponding, lower adders, analog-to-digital converter, whose information input is the input of the autocorrelator then. a output is connected to the information input of the memory block; the control of the analog-digital converter and the memory block are combined and connected to the output of the pulse generator; the formation of factors, a frequency divider into two and three inputs, which are combined and connected to the output pulse generator, the outputs of the dividers are connected respectively to the first and second control inputs of the formation units of factors, the first and second outputs of which are connected respectively to the first and second inputs of the corresponding th block multiplication, 3; , 1, 2, ..., M-1 information inputs of each block of formation of factors are connected to the outputs of the corresponding cells of the memory block, the output of which is connected to the two inputs of the first multiplication unit. In addition, the j -th factor formation block contains the OR element, a counter, a trigger, an adder, a memory unit with 3J cells, and two AND elements whose inputs are the first and second control inputs of the factor formation block whose outputs are respectively, the outputs of the adder and 2.J are the cells of the memory block, the first and second outputs of the trigger are connected to the second inputs of the corresponding AND elements, the outputs of which are connected to the corresponding inputs of the OR element, the output of which is connected to the input of the counter, the output which is connected to the trigger input and the first control input of the memory block, whose information inputs are the information input of the multiplier formation unit, the second control input memory block is connected to the output of the second element I. In FIG. Figure 1 shows the structural electrical circuit of a digital autocorrelator; in fig. 2 is a block diagram of the j-th factor formation unit; in fig. 3 is a table corresponding to the contents of the input memory block. The device input is sequentially connected to the first input of analog-digital converter 1 and the first input of input memory block 2, the second input of which is combined with the second input of analog-digital converter 1 and divisors 3 and 4, respectively, by two and three and connected to output 1 nerator 5 pulses. 3) informational 9 inputs of each j-th block 6 of formation of factors (j 1, 2, ..., M-1) are connected to the outputs of the corresponding cells of the input block 2 of the memory, similar to the first one. The first and second control inputs of the blocks 6 forming the factors are respectively combined and connected to the outputs of the frequency dividers respectively by two 3 and three 4. The first and second outputs of the forming blocks 6 are connected respectively to the first and second inputs of the corresponding multiplication unit 7, starting from the second block 7 multiplying, which through the corresponding adders 8 are connected to the corresponding outputs of the device. FIG. 2 shows a structural electrical circuit of the j-th block 6 of formation of factors. The first and second inputs of the j-th formation block 6 are the first inputs of the first and second logic elements AND 9 and 10, respectively. The output of the second logic element AND 1O is serially connected to the first input of the logic element OR 11, the input of the counter 12, the first control input of the buffer block 13 memory. The output of the first logical element AND 9 is connected in parallel to the second input of the logical element OR 11 and the second control input of the buffer memory unit 13. The second inputs of the first and second logic elements AND 9 and 10 are connected respectively to the direct and inverse outputs of the trigger 14, the input of which is connected to the output of the counter 12. The output of the Lj cell of the buffer memory 13 is the first output of the i-th generation block 6 , and the output of the j-th and 3 j-th cells are connected respectively to the first and second inputs of the adder 15, the output of which is the second output of the j-th formation block 6. The digital autocorrelator works as follows. The A / D converter 1 performs time sampling of the input signal using a clock pulse generator 3 pulses, which, in addition, receives the sampled signal in the first cell of the input memory block 2 and shifts the contents of the cells of the input memory memory block 2. With the arrival of the first clock pulse, the first sampled signal is received in the first cell of the input memory block 2.

and the first block 7 multiplies the adder 8, in which squaring of the incoming signals and the accumulation of their sum takes place, starts working. The cycle of operation is repeated with the arrival of each subsequent sync pulse. In accumulator 8, the sum accumulates

 ; eo

L-

where is the input process value, N is the input process sample size.

With the arrival of the second clock pulse for the first time, the frequency divider is triggered by three 4 and nepBbfft factor 6 formations receive the signals located in the first three cells of the input memory block 2. The cycle of operation of the first block of 6 formation

The factors are repeated through two clock pulses, after which the frequency divider triggers to two 3, and the first formation unit 6 receives the signals from them located in the first three cells of the input memory unit 2. In this case, for two sync pulses, the first generation unit 6 forms a pair of factors and transmits them to the second multiplication unit 7 and the second adder 8, where the sum- corresponding to the second point of the correlation function, etc., accumulates until the last sync pulse arrives.

The blocks of formation of factors work as follows. In the initial state, the triggers 14 of the formation blocks 6 (Fig. 1) are in the zero state. Thus, it permits the passage of sync pulses through a logical element AND 1O from the frequency divider by three 4 and prohibits the passage of sync pulses from the frequency divider by two 3 (Fig. 1) through the first logical element AND 9. With the arrival of the 3 j -th sync pulse in and - the volume of the formation unit 6 triggers the counter 12 with the conversion factor j and outputs a signal to the first control input of the buffer memory 13, thereby allowing reception of the contents of the first 3J cells of the memory input memory 2 into the buffer memory 13.

In this case, the signal from the output of the counter 12 is fed to the input of the trigger 14, setting it to one state, thereby allowing the clock to pass from the frequency divider to two 3 (Fig. 1 through the first logical element And 9

on the second control: the common input of the buffer memory block 13 and through the logic elements OR 11 into the counter 12 with the conversion factor J. For the Facts formed by 2J clock pulses, And shifts in the cell contents occur in the buffer block 13 of the memory, summation occurs in the adder 15, and pairs of factors are transmitted to the first and second outputs of the j - / that formation block.

 ,,

-j-h

and

X

  (one)

 i) Thus, for 2 j sync pulses in the j +1 ohm adder 8 (Fig. 1) and at the D +1th output of the device, the sum

i / j.,. x.j, -). (3)

Since the cycle of operation of the j-th block of the formation is repeated after 2i, it is possible to record the margin for the sum that is accumulated in the + 1st adder,

8 per l sync pulses:

N j

, 4 i / i-i KX ig - j.i / iej) ,.

where N; i can be determined from the condition, lj4-i4-aN J MPri 1) we have

H-.i

(five)

iN,

It can be shown that (4} is an estimate of the correlation function at the j-9th point when multiplied by 1 / C. 1 / N-2-f,

From (3) you can determine the time required to process a single input

 signal4- 4.7 + 5

)

it. - To finish the operation of the device, it is required (S + 2IVV) clock pulses, then the total operation time of the device will be equal to -t f.

- CN + -2M) tc.2. , S /, -. h, l

Claims (2)

--T- X hp // It can be shown that the speed of the proposed device is higher in cf.) avenenike with approximately two times known, taking into account that AL. To explain the operation of the device in FIG. 3 shows a table corresponding to the contents of the input memory block, the buffer memory block 13 {FIG. 2) j adder 15 (Fig. 2), a block 7 multiplying (Fig. 1) for the 4th ordinate of the correlation function, i.e., for j 4, clock pulses from the generator 5 pulses (Fig. 1). The technical realization of the device can be implemented using digital computer elements. The ADC 1 is determined by the given accuracy of the estimate of the correlation function and the device speed. The input memory unit 2 is a set of shift registers. The number of shift registers is equal to the number of ADC bits 1, and the register size is equal to the number of ordinates of the correlation function -M. The frequency divider by two 3 is a trigger on the counting inputs. The frequency divider by three 4 can be flashed as a two-digit counter with a scaling factor of 3. Multiplication blocks 7, adders 8 (Fig. 1), AND 9 and 1 O OR 11 logic elements, counter 12, trigger 14, adder 15 (Fig. 2), being the usual nodes of the PCV, can be performed on integrated circuits. The first multiplication unit 7 is a quad. Moreover, the speed of the quad can be done much better than the speed of a multi-device. Therefore, the speed of the first multiplier does not affect the overall speed of the device. The buffer memory block 13 (Fig. 2) is a device similar to the input memory block 2 (i-p. 1 Using new elements of frequency dividers for two and three and forming units, multipliers containing two logical elements I, logical elements OR, adder, trigger, counter and buffer memory block allows to increase the speed of the parallel action correlator by reducing the number of multiplication operations, which allows to approximately double the ADC polling frequency, i.e. to extend the frequency range of the device and vysit efficiency correlation analysis in real time. Claim 1. Digital auto-clerk, sbashshy M multiplication blocks, the outputs of which are connected to the inputs of the corresponding adders, analog-digital generator, information input which is the input of the autoregulator, and the output connected to the information input of the memory block, control inputs to the analog a digital converter and a storage unit are combined and connected to the output of a pulse generator, characterized in that, in order to increase speed, an M-1 factor formation unit is inserted into an autocorrelator, Frequency dividers for two and three, the inputs of which are combined and connected to the output of the pulse generator, the outputs of the dividers are connected respectively to the first and second control inputs of the multiplier formation units, the first and second outputs of which are connected respectively to the first and second inputs 3 -; ; j 1, 2, ..., M-1 — the information inputs of each block of formation of factors are connected to the outputs of the corresponding cells of the memory block, the OUT of the first of which is connected to the two inputs of the first multiplication unit. 2. The autocorrelator of claim 1, which is based on the fact that —and a block (| the lawyer of the multipliers contains the element OR, the counter, the trigger, the totalizer, the memory block with 3J cells and two AND, the element AND whose inputs are The first and second control inputs of the multiplier formation unit, the outputs of which are the outputs of the adder and 2 3 -measures of the memory block, the first and second outputs of the trigger, respectively, are connected to the second inputs of the corresponding elements AND, the outputs of which are connected to the corresponding inputs of the OR element which exit th input is connected to a counter whose output is connected to the input of the first flip-flop and the control input of the memory block, information which is input; :) are an information input unit forming factors, the second 9Y6V81Y10 control input of the memory block connection -1. USSR author's certificate chen to the output of the second element I. Sources of information taken into account in the examination No. 590762. Cl. GO6F 15/336, 1976. 2. Gribanov Yu. N. et al. Automatic digital corsel tori. M., E er 5 gi, 1971. p. 150