SU960846A1 - Adapting coding converter of stationary random processes - Google Patents

Description

one

The invention relates to automated control and monitoring systems and is intended to reduce redundancy when encoding stationary random processes.

A device for adaptive coding with prediction is known.

However, such a device requires an a priori knowledge of the characteristics of the process being coded or the introduction of a predictive device into the circuit, which causes high hardware costs. ..

The closest to the proposed technical entity is an adaptive coding device containing an adder, an analog-to-digital converter, whose input is the device's input, and the outputs are connected to the first group of switch inputs and the corresponding inputs of the statistical maximum and minimum units of the output, the outputs of which are connected respectively with the second.

a group of inputs of the switch and with the first group of inputs of the adder., the second group of inputs of which is connected to the corresponding outputs of the switch. The outputs of all the bits of the adder are connected to the first group of inputs of the additional switch, the outputs of the higher bits of which are connected to the corresponding inputs of the zoom short circuit blog, the outputs of which are connected respectively to the second group of inputs of the additional switch, the output of which is device 2 output.

15

 A disadvantage of the known device is its hardware complexity due to the use of blocks of statistical evaluation of the maximum and minimum, each of which consists of n-fold 20 memory registers and a digital one. comparison devices, as well as a switch of two n-bit information flows. 3S6o The purpose of the invention is to simplify the device. This goal is achieved by the fact that an adaptive coding converter containing an analog-to-digital converter, whose information input is the information input of the adaptive coding converter, and a synchronizing input connected to the synchronizing output of the control unit, an adder, the bit outputs of which are connected to the information inputs of the switch corresponding to -enocally, and the outputs of the senior groups. Disks - to the information inputs of the block. determining the scale corresponds to: Venno, which controls the input The control unit's record management output is connected to the scale of the control unit, and the outputs are the first group of outputs of the adaptive coding converter and connected to the control inputs of the switch, respectively, the outputs of which are the second group of outputs of the adaptive coding converter, a register, a reversible counter and a memory block, and reversible the counter is connected to its information inputs with the analog inputs of the analog-to-digital converter with a responsible, summing, subtracting setting and synchronizing control inputs with control outputs of summation, subtraction, installation and synchronization outputs of the control unit, respectively, and the outputs of the reversible counter are connected respectively to the inputs of the first group of the adder, information, register inputs and to the address inputs of the memory block, the control and information inputs of which are connected with the output of the record-playback control output and the output of the counting pulses of the control unit, respectively, the start input of which is an additional input of the converter, the first and the second inputs of the control unit are connected respectively to the overflow output of the reversible counter and the output of the memory unit, the write control output to the control unit register is connected to the control input. register, the group of outputs of which is the third group of outputs of the adap. tive coding converter and connected to the inputs of the second group of the adder, respectively. In addition, the control unit contains five RS-flip-flops, four OR elements, eleven AND elements, two subtractive pulse counters and a counting pulse generator, the S input of the first trigger, which is the control input trigger input, is connected to the first input of the first OR element and the control inputs of the first and second counting pulse counters, the R input of the first trigger, which is the first input of the control unit, is connected to the S input of the second trigger, whose R input and S input of the third trigger are connected to the overflow output of the first second subtractive pulse counter, the second input of the control unit is connected to the first inputs of the first, second, third and fourth elements And, the output of the first element And is connected by the cR-input of the third trigger, the output of the second element And is connected to the 5th input, and the output of the third element And R-input of the fourth trigger. the output of the fourth element I is connected to the S-input of the fifth trigger, the R-input of which is connected to the overflow output of the second. subtractive pulse counter, the first inputs of the fifth, sixth, seventh, eighth, ninth, tenth and eleventh elements are combined and connected with the output of the counting pulse generator, the second input of the fifth element I is connected to the forward output of the first trigger, the inverse output of which is the output of the counting pulses of the control unit, the second input of the sixth element I is connected to the forward output of the second trigger and the second input of the tenth element AND, the inverse output of the third trigger is the output of the write control to the register, and the direct output of the third trigger is connected to the second inputs of the second AND element, the seventh AND element, and the first OR element, the output of which is the installation output the control unit, the direct output of the fourth trigger is connected to the third input of the first element OR and the second inputs of the third, fourth and eighth elements AND, and the inverse output of the fourth trigger, which is the output of the control recording scale n with the second input of the first element AND, the direct output of the first trigger is connected to the second inputs of the ninth and eleventh elements AND, the output of the fifth AND element is connected to 59 the first inputs of the third and fourth elements OR, whose outputs are respectively the summation control output and a record control playback output of the control unit, the output of the sixth AND element is connected to the second input of the fourth OR element and to the first input of the second OR element, the output of which is the clock output of the control unit , the output of the seventh element is connected to the second input of the third element OR, the output of the eighth element AND is the control output of the control unit subtraction, and the output of the ninth element AND is connected to the second input of the second element OR, the outputs of the tenth and eleventh elements AND are connected to the counting inputs, respectively first and second subtractive pulse counters. FIG. 1 shows a block diagram of an adaptive coding converter; in fig. 2 - structure of the number recorded in the memory block; in fig. 3 structural scheme for determining the scale; in fig. i same control unit. The converter contains an analog-to-digital converter (ADC) 1, control block 2, register 3, reversible counter, memory block 5, summator 6, scale determining block 7 and switch 8. Control block 2 contains the element OR 9 elements AND 10-13, RS-three heres, elements AND 19-23, elements OR, generator 27 counting pulses, elements AND 28 and 29 subtractive counters 30 and 31 Scale determination unit 7 contains drivers 30, elements AND 33, and a storage register H Control unit 2 is built on based on a synchronous control automaton (UA) with rigid logic, for the function of which is determined by the time relations between the input and output signal sequences necessary for a particular device. In the subtractive counters 30 and 31, the code is preset. The sets X, B, C are sets of input signals, where X XQ, x, XQ J are the set of input signals YY, x is the trigger signal; x is the signal of the end of cleaning of the memory unit (PSU); x is the sign detection signal Xmin X ax46 B b, ..., b, is the code of the number of samples in the adaptation cycle, which determines its duration. With CT,.,., C is the code of the number of samples in the adaptive coding cycle (DI measurement), which determines its duration. Sets B and C are specified by dialing a code and written to the counters by the signal Xd. The set A ad,. ,,, а4 is the set of states of the АА, which determines the sequence of operation of the converter, where а is the cleaning of the power supply; a-, - adaptation cycle; a -, - definition and definition of scope and scale of M; a is an adaptive coding cycle. The set VO UO, U. the set of output signals UA, controlling the operation of the converter; where ud is the ADC clocking, recording the parallel code from the ADC output to the reversible counter (PC); y - giving of counting pulses to the summing input of counter 4; y, - giving of counting pulses to the subtracting input of the counter k; at, - installation in About the counter 4; installation of memory block 5 in the write (read) mode; y feeding logical 0 and 1 to the input of memory block 5; y — write the value of X to register 3; Y- | recording the value of M in block 7 for determining the scale. The input of the scaling unit 7 is given to (nS) most significant bits from the output of the adder 6. When the output of the adder 6 has an expansion code, it is converted into a scale value M in binary code, which is the number of the higher digit containing logical 1, in the group of bits at the output of the adder, respectively, from (S + l) -ro to the n-th. The scale code M is stored by the control unit 2 in the DF and during the adaptive coding cycle acts on the control input of the switch 8. The number of outputs and, accordingly, the bits of the DF is defined by the expression m log- (n-S + 1), where (n-S + l) - the total number of scales. Scheme 7 for determining the scale corresponds to the values of ri 12, S 5, m 3. The adaptive coding process consists of two cycles: an adaptation cycle (duration T) and an adaptive coding or measurement cycle (duration T). The stationary random process, represented at the output of the ADC, is an n-bit binary code. In the adaptation cycle, the number of one-bit cells of the memory block is equal to the number of gradations (quantization levels) of the ADC. All cells of the memory block are pre-recorded with a logical O. When encoding each value of a random process, logical 1 is written into the corresponding cell of the memory block. By repeating the code at the output of the ADC, logical 1 is confirmed in this one. After completion of the adaptation cycle, the cells of the memory block turn out to be a recorded sequence of the form 00 ... 011 .... 1100 .... 00 (Fig. 2), where the bit number of this sequence corresponds to the cell address of the block, the memory that characterizes the minimum and maximum values of a random process, as well as the range of its change. The determination of the maximum and minimum values of a random process is carried out in the mode of reading information recorded in the memory block. When reading information from cells with consecutively increasing addresses, beginning with zero, the number of memory cells containing logical O (cells with addresses O – K in Fig. 2) is counted. When the first logical 1 appears at the output of the memory block, the counting stops, and the resulting number is the minimum value of the random process. The maximum value of the random process is determined similarly when reading information from cells with successively decreasing addresses occurrences of the first logical 1 at the output of the memory block. The number of cells in the memory block that contains logical O (the cells with addresses (P + 1) - () in FIG. 2) is the maximum value of the random process. The obtained values of X allow us to determine the range of fluctuations of the random process (span) as the difference -X, y,), as well as the May code of values (X picnT minb and M staff (t binary bits) division price. Depending on the magnitude of the scale code The circuit is rearranged in such a way that S bits (where) are connected to the output of the adaptive coding converter from the n-bit representation of the magnitude of the scale, starting with the most significant bit. The magnitude of the division price dX is related to the scale M by the relation DH 2., (1) In the adaptive coding (measurement) cycle, an analog-to-digital conversion of the input signal X (t) and from the resulting code (n bits) of each ordinate x, the value (n bits) determined in the adaptation cycle is subtracted, and the values of the ordinates of the newly shifted random process y (t) Y X, - X are obtained. S is a binary code with a division value corresponding to the scale M defined in the adaptation cycle. The number of bits S is selected in accordance with the required measurement accuracy. As a result of adaptive coding, at the output of the converter, an array of sample values of the stationary random process Z (t) is defined, defined as% i -, .. i. Obviously, you can restore the original random process in accordance with the expression. codes in the counters 30 and 31 and setting the AU in the state a 1 (a O, a, jj 0), which corresponds to the sequential appearance at the output of the signals y, Y (0), y (write), y. In this case, at the outputs of the bits of the reversible counter k (its capacity is equal to the number of cells in the memory block), address codes are formed, starting with zero and above, by which logical O is recorded in the corresponding BP cells, i.e. the block is cleared ka memory.

The appearance of the signal x., At the output P of the counter H overflow, indicates the end of cleaning.

On the signal x, the UA is set to the state a -1, which corresponds to the sequential appearance of signals ygCl), y (write), PP, as well as the feeding of counting pulses to the subtracting input of the output signal 30 at the output. the clock pulse triggers the A / D converter, records the result of the previous measurement from the A / D output in counter i, records at the corresponding logical address 1. State AA corresponds to an adaptation cycle, the end of which is indicated by the appearance of signal P at the corresponding output of counter 30.

By the signal P arising from the overflow of the counter, the UA is set to state a ,, 1, which leads to the sequential appearance at the output of the signals beats, (reading), y, y /. At the same time, at the outputs of the counter k, consecutively increasing addresses of the memory unit are formed, starting from zero, from which the information is read as logical O. At the output of logical 1 (signal xj), the counting pulses on the PC stop and the number X is formed in it which, by. signal y is rewritten to register 3

The signal X is used to set the UA to state a 1, which causes a consistent appearance of the signals y, y (read), y, y on the output. At the outputs of the counter C, consecutively decreasing addresses are formed, starting from the highest, from which information is read as logical O. When a memory 1 is output at the output (XQ signal), the control signal y is generated in the control block, the counting pulses are fed to the counter k is terminated, a number equal to is formed in it. The latter arrives at the first group of inputs of the adder 6, to the second group of inputs of which is fed Xf from the output of the register 3. At the output of the adder 6 there is a difference (Xj jXmin) - the oldest (nS) bits of which go to block 7 for determining the scale, in which the value of the M code, fixed by the Y- signal from the control unit, is determined.

If in all (nS) most significant bits of the swing code at the output of the adder 6, the signal is logical O, then M is 0. If logical 1 is only in (S + 1) -M bits, then M 1. If oxy 1 is in (5 +2) th discharge, and the state (S + O-ro discharge indifferent, then M 2 and so on.

Obviously, the total number of as-scales is (n-S + 1).

In accordance with a specific value of the scale code M coming from the scale determining unit 7, S bits of the n-bit binary code from the output of the adder 6 are connected to the output of the switch 8 as follows: for М О (fluctuation range X (t) less than 2) connect the output of the switch B from the 1st to the Sth low-order bit from the output of the adder. 6; when M 1 (fluctuation range X (t) is smaller), the output of switch B is connected from 2nd to (S + 1) -ro low-order bit from the output of adder 6, etc.

This is where the adaptation cycle ends.

Then, the AA is set to the a4 state, which corresponds to the adaptive coding cycle.

In the cycle of adaptive coding ordinates of process X (t) from the output of the A / D converter 1, a reversible counter is fed to the first inputr group of the adder 6, to the second input group of which the code of the process minimum arrives. At the same time, at the output of the adder 6, in each clock cycle of the A / D converter 1, a difference is formed between the current ordinates xj; and the minimum value determined in the adaptation cycle. This difference y at the output of the adder 6 is represented at the output of the switch 8 as Z-in accordance with formula (3).

Thus, regardless of the fluctuation range of the encoded process X (t), the result of the adaptive coding Z is represented accordingly. with the formula (3) S-bit binary code.

Claims (2)

In addition, the output of the adaptive auditing transducer contains the values of Xm. N (n binary digits) and the scale code M (n binary arcs), which determines the division price according to formula (1). The implementation of an adaptive coding converter is technically convenient and economically beneficial on large and medium integrated circuits mastered by industry. The proposed adaptive coding converter is simpler, known while maintaining accuracy of conversion and increasing reliability. Claims. 1. An adaptive coding converter of stationary random processes containing an analog-to-digital converter, the information input of which is the information input of the adaptive coding converter, and a synchronization input connected to the synchronization output of the control unit, an adder, the bit outputs of which are connected to the information inputs of the cogmutator, respectively the outputs of the group, the higher bits - to the information inputs of the scale unit, respectively, the control input of which is It is compatible with the output of the control record of the scale of the control unit, and the outputs are the first group of outputs of the adaptive coding converter and are connected to the control inputs of the switch, respectively, the outputs of which are the second group of outputs of the adaptive coding converter which, in order to simplify, contains a register, a reversible counter and a memory block, and the reversive counter is connected to information inputs with outputs of an analog-digital converter, respectively, s worlds that read, set and synchronize inputs — with the summation, subtraction, setup and synchronization outputs of the control unit, respectively, and the outputs of the reversible counter are connected respectively to the inputs of the first group of adder, information inputs of the register, and to the address inputs of the memory block, the control and information inputs of which are connected to the outputs of the control of recording and playback and the output of the counting pulses of the control unit, respectively, the start input of which is In addition, the first and second inputs of the control unit are connected respectively to the overflow output of the reversible counter and the output of the memory unit, the write control output to the register of the control unit is connected to the control input of the register, the output group of which is the third group of adaptive outputs coding transducer and connected to the inputs of the second group of the adder, respectively. 2. The converter according to claim 1, characterized in that the control unit contains five RS-flip-flops, four OR elements, eleven AND elements, two subtractive pulse counters and a counting pulse generator, the S-input of the first trigger, which is the start input the control unit is connected to the first input of the first OR element and the control inputs of the first and second subtractive pulse counters; the R input of the first trigger, which is the first input of the control unit, is connected to the S input of the second trigger, whose R input and S are input of the third trigger Ina with the overflow output of the first subtractive pulse counter, the second input of the control unit is connected to the first inputs of the first, second, third and fourth elements AND, the output of the first element AND connected to the R-BXO of the third trigger, the output of the second element AND is connected to the S input, and the output of the third element I.- to the R-input of the fourth trigger, the output of the fourth element I is connected to the S-B of the fifth trigger, the R-input of which is connected to the overflow output of the second subtractive pulse counter, the first inputs of the fifth, sixth, seventh, eighth Second, ninth and eleventh elements I are combined and connected to the output of the counting pulse generator, the second input of the fifth element I is connected to the forward output of the first trigger, the inverse output of which is the output of the counting pulses of the control unit, the second input of the sixth element I connected to the direct output of the second trigger and the second input of the tenth element AND, the inverse output of the third trigger is the output of the write control to the register, and the direct output of the third trigger is connected to the second inputs of the second element AND, the seventh element AND, the first element OR, whose output is the installation output of the control unit, the direct output of the fourth trigger is generic to the third input of the first element OR and the second inputs of the third, fourth and eighth elements AND, and the inverse output of the fourth trigger, is The control output of the scale is connected to the second input of the first element AND, (the forward output of the first trigger is connected to the second inputs of the ninth and eleventh elements AND, the output of the fifth element AND is connected to the first inputs of the third and solid elements OR the outputs of which are conformed. The output of the summation control output and the control output of the reproduction of the control unit, the output of the sixth AND element is connected to the second input of the fourth OR element and the first input of the second OR element, the output of which is the synchronizing output of the control unit, the output of the seventh AND element, is connected to the second input of the third OR element, the output of the eighth element AND is the control output of the subtraction of the control unit, and the output of the ninth element AND is connected to the second input of the second element OR, the outputs of the tenth and eleventh elements And are connected to the counting inputs of the first and second subtractive pulse counters, respectively. Sources of information taken into account in the examination 1. The author's certificate of the USSR No. 293239, cl. e 06 F 5/02, 1969. 2. USSR author's certificate №, cl. G 06 F 15/36, 1979 (prototype). ie A  m, in; - Kil "eS: "four - “W“ s a, r, f "ffl VJ .- “vj“ i .-ZHYG. L - “s, E . .1 “tag Ij S Ml "e  ff "V4 la (..I U..I II Cells - Si / imbi SfiOKO memory Fig.Z