SU959287A1 - Apparatus for registering flow of errors in discrete communication channel - Google Patents

Description

(54) DEVICE FOR DETAIL REGISTRATION OF A FLOW, ERRORS OF A DISCRETE CHANNEL OF COMMUNICATION

one

The invention relates to telecommunications and is intended to explore discrete communication channels.

A device for recording errors of a discrete communication channel, s {x-, connected in series to a command generator, an analyzer of unaffected characters, whose output is connected to the first, second and third inputs of a controlled switch, is known, to the first upstream input of which is connected the first the output of the write and read control block, as well as the error counter, clock generator, and registration block ..

However, the known device does not provide element-by-element recording of the error stream in high-speed data transmission systems.

The purpose of the invention is to improve the accuracy of 20 by element-by-element registration of the error stream in high-speed data transmission systems.

The goal is achieved by the fact that the device for registering the error stream of a discrete communication channel, containing sequentially connected driver, an analyzer of unaffected characters, the output of which is connected to the first, second and third inputs of the controlled switch, to the first control input of which is connected the first output of the control unit recording: and reading, as well as an error counter, a clock generator and a registration block, a shaper of time blocks, an analyzer of affected combinations, a distribution analysis block are entered error division, sequentially connected delay unit and OR element, as well as a memory unit whose output is connected to the first input of the registration unit, to the second input of which the output of the OR element is connected, and the output of the registration unit is connected to the first input of the recording and reading control unit, the second and third outputs of which are connected to the first and second inputs of the memory unit, and the fourth output of the recording and reading control unit is connected to the second control input of the controlled switch, the output of which is connected to retemu entry storage unit, and the fourth, fifth and sixth inputs of the control switch respectively connected the first output of the analyzer affected combinations error distribution analysis unit output and the output of the error counter, a first input of which is combined with the first inputs. A command generator, an error distribution analysis unit and a combination analysis analyzer, the second, third and fourth outputs of which are connected respectively to the third control input of the controlled switch, the second input of the error counter and the second input of the error distribution analysis unit, to the third input of which, as well as the first input of the clock generator is connected to the second input of the non-reflected character analyzer, the second and third outputs are connected to the second inputs of the recording control unit and to match the analyzer of the affected combinations, to the third input of which, as well as to the third input of the writing and reading control unit and to the input of the command driver. connected to the first input of the time block maker, the second output of which is connected to the fourth input of the write and read control block, and to the inlet of the time block former, to the second input of the OR element and to the fifth input of the write and read control block, the second output of the command coder, the second output of the analyzer of unaffected characters is connected to the sixth input of the writing and reading control unit and to the input of the delay unit. FIG. 1.the device’s structural diagram is presented; in fig. 2 - error flow registration form on punched tape. A device for registering an error stream of a discrete communication channel contains a driver 1, an analyzer 2 unaffected characters, a write and read control block 3, a memory block 4, a time block builder 5, a clock generator 6, a stripe combination analyzer 7 controlled by a switch 8 , error counter, block 10 analysis of the distribution of errors, block 11 delay, the element OR 12, block 13 registration. The device works; as follows, In the absence of errors in the communication channel, the analyzer of 2 unaffected characters, consisting of three counters and the block 3 of the control for recording unaffected characters, counts the number of clock cycles at a speed corresponding to 9.6 kbit / s. Clocks are supplied from the first generator output of 6 clocks. When the fields are full: the analyzer counters have 2 unaffected characters (12O1120х120) from its output 2, a command is sent through the delay unit 11, and the OR 12 element, which starts the registration unit 13 (the perforator motor). The delay, equal to 8OO ms, is necessary for the full acceleration of the perforator motor. The command from the output 2 of the analyzer 2 unaffected characters is also fed to the input b of the write-and-control unit 3, from the third output of which the signal is prepared by the preparation unit. 4 memory to write. Memory unit 4 consists of 1603U (two subunits of 8 RAM each), two address control counters, and a switch for controlling RAM modes. There are three modes of RAM: storage, writing, counting. The 4th unit of operation is working in such a way that one 8OZU is recorded, from another the WHO is connected. Simultaneously with the signal being sent to the memory block 4, the output from the 1-block 3 of the write control and the read signal is fed to the control input of the 3 switch 8, which connects the I, 2 AND 3 information inputs of the controlled switch to the information output 1 of the analyzer 2 unaffected characters, and then further through the switch 8, consisting of eight bits, the unaffected characters are recorded in the memory block 4. Information about correctly received characters at certain times is overwritten to punched tape (Fig. 2a). Three rows of five holes are punched on a punched tape: four lines carry information, the senior (fifth) bit is marking. At the time of error, the signal Error arrives at the first inputs of the formatter 1 command, the analyzer 7 affected combinations, block 10 analysis of the distribution of errors and the counter 9 errors. The command shaper 1 gives the output of the output l command to prevent the counting of takov on the analyzer 2 unaffected characters . From output 2 of starting shaper 1, a command is issued to start a shaper of 5 temporary blocks, forming a 1 Kbyte word, and a Word of 32 bytes length, from the same output, the command to start the motor 13 of the registration unit (the perforator ), as well as this command is fed to the input B of the write-and-read control unit 3. From the output 3 of the recording and reading control unit 3, a signal is fed to the input 2 of the memory 4, which prepares one subunit of the memory 4 for recording and the other for reading. From the second generator output of 6 clocks to input 2 of read write control unit 3, clocks arrive with a speed corresponding to 72 speeds from output 4 of write write control unit 3 and a signal is received to control input 2 of controlled switch 8, which from all eight bits controlled switch 8 One from the switch input 7 enters the 3 address of memory block 4, which corresponds to three lines of punched tape puncturing (Fig. This color characterizes the arrival of a fault. At the same speed, the number of of affected characters before the arrival of an error from the output of the analyzer 2 Unprotected characters per l, 2 and 3 inputs of the controlled switch 8 Data on the number of correctly received characters are received in the next three addresses of memory block 4 (Fig. 2-c). The address of the memory unit takes place in a time less than the time taken to follow two cycles (72 kbps 9.6 kbps), due to which no loss of information occurs. Upon the arrival of an error, the analyzer 7 affected combinations consisting of two counters block and block, and block 1O analysis of the distribution laziness mistakes. At the input 2 of the analyzer 7 affected combinations from the output 3 of the generator 6 cycles, clock cycles with a frequency of 9,600 bps are received; 8 due to which by the analyzer 7 bytes (1 byte 8 bits) are generated by the affected combinations. Analyzer 7 affected combinations analyze generated bytes, and at output 1 of analyzer 7 affected combinations the information about the number of affected byte appears. The error distribution analysis unit 10 is a register. The frequency corresponding to 9.6 kbit / s, coming from the output of the J / 6th generator, to the input 3 of the U unit of the error distribution analysis, is necessary to advance the register. At the output of b; yun; and 1O, the error in the affected byte appears elementwise. Inputs 4 and 5 of the controlled switch 8 are sequentially connected respectively to the output 1 of the analyzer 7 affected combinations and to the output of the error distribution analysis unit 1O. The data on the number of the affected byte and its distribution is recorded through the switch 8 into the memory block 4, which corresponds to the printout (FIG. 21). Due to the fact that the analyzer 7 outputs the number of the ported byte only and is analyzed symbolically by the infected byte, Idforma10gi occurs. Analyzer 7 affected combinations (the number of affected bytes is also shown by luminously issuing the number of affected bytes. If the number of affected bytes is greater than 15, i.e. the transfer is worse than IQ, then 4 analyzers of the affected combination receive incoming block 2 of block 10 (distribution errors) and the command is given Yes Resolution from output 3 of the analyzer 7 affected combinations to input 2 of counter 9 errors. Counter 9 errors starts counting the number of errors in a block with a 32-byte error when the first error arrives, and how the output of this block information appears on the command Resolution from the analyzer 7 affected combinations. From the output 2 of the analyzer 7 affected., the command is sent to the control, the input of the 3-controlled switch 8, through which the input 6 of the switch 8 is connected to the output of the counter 9 error, С1 $ gnal About the end of the block 32 bytes long — from output 2 of the former 5, through the recording control and matching module 3 comes to the control. 2 input 2 of the switch 8, according to which the data on the number of 32 bytes enters the memory 4 block 4 that is appropriate for printing ke (FIG. 25). The recording of the number of errors in blocks with a length of 32 bytes continues to the word for 1 kilobyte. Signal about the end Words with a length of 1 kB from code 1 of the driver 5 blocks, the HS input 5 of the write control block 3 is read and read. This signal from output 2 of the recording control unit and coupling is received — a memory command arrives at memory 4, preparing one subunit of memory 4 for reading, and the other for recording. The registration unit 13 in the full cycle of its operation generates synchronization signals from the output of the registration unit 13 to the input 1 of the write and read control unit 3. The last, at the corresponding moments of the operation cycle of the registration unit 13, from output 2, submits a command to rewrite data from memory unit 4 to the tape of registration unit 13 (Fig. 2). At this point, the motor of the registration unit 13 is fully revving. The signal about the end of the word also enters the input 3 of the analyzer 7 affected combinations and brings it to the original state, and the same signal, entering input 2 of the driver 1, also translates it is in original condition. The proposed device provides element-by-element registration of the flow of erroneous symbols in high-speed data transfer systems without losing information while preserving the continuity of the recording, which allows greatly expanding the possibility of the learned static material, making it more universal. Data recording takes place on a perforator operating in start-stop mode with the motor starting at certain times, which increases the reliability of the device and reduces noise from the puncher to a certain extent. Form of the Invention Device for registering a discrete communication channel error stream containing serially connected command generator, analyzer of unaffected characters whose output is connected to the first, second and third inlets of the controlled switch, to the first control input of which is connected the output of the write and read control block, as well as the error counter, clock generator, and registration block, characterized in that, in order to improve the accuracy by element-wise register of the error stream in high speed transmission systems, a shaper of time blocks, an analyzer of affected combinations, an error distribution analysis block, a serially connected delay block and an OR element, as well as a memory block whose output is connected to the first input of the registration block, the second input of which is connected to the OR element, and the output of the registration unit is connected to the first input of the recording and coupling control unit, the second and t) outputs of which are connected to the first and second inputs of the memory unit, and the fourth output the write and read control unit is connected to the second control input of the controlled switch, the output of which is connected to the third input of the memory block, and the fourth, fifth and sixth inputs of the controlled switch, respectively, the first output of the analyzer of affected combinations, are connected to the output of the error distribution analyzer block JI output of the error counter, the first input of which is combined with the first inputs of the command driver, the error distribution analysis unit and the analyzer of the affected combinations, the second, third and even pairs the outputs of which are connected respectively to the third control input of the controlled switch, the second input of the error counter and the second input of the error distribution analysis block, to the third input of which, as well as the second input of the unaffected characters analyzer, the second and third outputs of which are connected respectively, to the second inputs of the recording control unit and reading and analyzer of affected combinations, to the third input of which, as well as to the third input of the recording control unit and reading and the second input of the command driver, the first output of the temporary block generator is connected, the second output of which is connected to the fourth input of the write control block; and the second input of the command generator, and the second output of the analyzer of unaffected characters are connected to the sixth input of the recording and reading control unit and to the input to the input of the temporary block generator, to the second input of the OR element, and to the fifth input of the recording and matching control unit. block zader zhi. Sources of information taken into account in the examination. 1. The USSR author's certificate number 650242, cl. H 04B 1/10, 1979 (prototype).

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Claims (1)

Claim An apparatus for registering discrete flow channel of communication errors, comprising serially connected for- ₄₀ tors, commands analyzer unaffected symbols output of which is connected to the first, second and third inputs of the controlled switch, to the first control input of which is connected per- vy output write and read control unit as well as an error counter, a clock generator and a recording unit, characterized in that, in order to increase accuracy by element-by-element registration of the error stream in high-speed systems For data transfer, a shaper of time blocks, an analyzer of the struck combinations, an error distribution analysis block, a delay unit and an OR element, as well as a memory block, the output of which is connected to the first input of the registration block, to the second input of which the output of the OR element is connected, are introduced , and the output of the registration unit is connected to the first input of the write and read control unit, the second and third outputs of which are connected to the first and second inputs of the memory unit, and the fourth output • of the write control unit ew and reading is connected to the second control input of the managed switch, the output of which is connected to the third input of the memory block, and the fourth output of the analyzer of the affected combinations, the output of the error distribution analysis block, the output of the error counter, the first input of which is connected to the fourth, fifth, and sixth inputs of the managed switch combined with the first inputs of the command shaper, the error distribution analysis unit and the affected combination analyzer, the second, third and fourth outputs of which are connected respectively, to the third control input of the managed switch, the second input of the error counter and the second input of the error distribution analysis unit, to the third input of which, as well as to the second input of the analyzer of unaffected characters, the first output of the clock generator is connected, the second and third outputs of which are connected respectively to the second inputs of the block recording and reading control and analyzer of the affected combinations, to the third input of which, as well as to the third input of the recording and reading control unit and the second input rmirovatelya commands connected first output driver temporary block, the second output of which is connected to a fourth input of the control unit zapisyuj and reading, and to the input of the temporary block to the second input of the OR gate and the fifth entry writing and reading control unit connected to the second output of '·. command shaper, while the second output of the analyzer of unaffected characters is connected to the sixth input of the write and read control unit and to the input of the delay unit. '