SU1320809A1 - Signature analyzer - Google Patents

Abstract

This invention relates to a technique for monitoring and diagnosing digital devices. The aim of the invention is to increase the reliability of the analysis, taking into account the actual distribution of possible errors in the output sequences of monitored discrete devices. Signature analyzer contains 1 clock pulse generator, counter 2, shift register 3, trigger 4, element OR 5, information input 6, setup input 7, control start input 8, information output group 9. Signature analyzer generates a signature by alternately convolving modulo two fragments of the controlled sequence. This method is based on the assumption of equal error of any multiplicity in a controlled sequence. The reliability of the control of this analyzer under this condition is higher than that of signature analyzers, built on shift registers with feedbacks through a modulo two. 1 il. you cl oo N5 About 00 about with

Description

13

The invention relates to the control and diagnostics of pyrphic devices and can be used in the implementation of technical means in these units.

The purpose of the invention is to analyze the reliability of the analysis taking into account the real distribution:; ohibo to output sequences of controlled discrete devices,

The drawing shows the functional diagram of signature aialysise,

The analyzer contains a generator of i clock pulses, a counter 2, a shift register 3, a trtgger 4. zlemait OR 5, an information input 6, a setup input 7 5 control, which, start, a group of parameters: x output 9,

Analyzer works;:, with t, about them - time.

Before the start -; work for the whole tribe ;; .- the memory of the signature analyzer is set to the initial state by the signal from the set-up input 7, and with the arrival of the minimum signal to the control input 8 of the recording, the clock frequency appears on the g, e of the generator 1. A series of counterchlanced signals, the driver of the test device’s discrete device, via the information input b postug ;; - em in: and the counting input of the trigger 4 ;, is modulo two and not available; r to the information input of the continuous recording of the shear regis gra 3

Counter 2 divides this succession into different fragments of a length of r. Result of convolution but MODULE

Г п two of each of I ----- hour-gay, where

P

Guest I recorded a register 3 with a signal nomeinzyu with k--; -; bit output of the counter ca 2 (k). In this case, one tempo

zeroes out the trigger time 4 After the fic :: a-t of the counter h; 1sl / hl of the discharge vg.hod about a hundred ga; i bots the generator of the clock name: p,

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 compare with h allo1n1. Pa C) Silyan 1st of this comparison is done ();:; about the morality of the sensible dsc-e device,

The proposed signature-based analyzer implements the method of f-shaping a slnat-ay, based on the 6 TOMj predlozhenie that in the output of the next 1-1 atno note: - a faulty -discrete device with a distinct probability -n-ω can read any error The multiplicity of the Dos G-lakes control of the proposed analyzer under this condition is given out, after signature analyzers, built on shear feedback registers of two.

Go rumla and 3 o b ete n i

Sl1gnaturp 1gy analyzer containing: 1PN generates u; :) taktovk impulsovg counter "Vigovo register flip-flop and an OR gate, pg.ichem grugn-ia-Infor- mation with vyhodot shift register is grupgoy nformadionnk ikhodov analizats RA 3 O tlichu y-rj and u with .eM, j -. then J with the task of increasing- 11: analysis taking into account the real leg-on ras.dredeleii possible Hf rX errors in; UHG: SINGLE PS SLS TO TABLE

ijoc-1 x cowl | 3olir-uem-s dnskretnB1x devices. 1-gnffor: analyzer ps input input) 1dkl; very accurate to the counting input - r t sller, the output of which is with; information; c) the sequential write of the register SDRIGSBO1O, the reset input of which is connected to the i.P. element and is - wiht the analyzer input, control-in-; 1 1 1; 1 nd BXOJ :, start-up; connected to the entrance of the zaggush geyetator 7 akto} 5th im-, vkots KCTCPOJ.-O is connected to

Log .-. T, where r is dpl-; and, and separate.-1st oparivienTa is controlled by smos jos. ;; s. G (}; p. I ej.bi i-jCTH .isaeMoro on -dulk; va} connect: s; I} 1khrovkh; to: h with ;. Nigevo1 about the register and :: second ;;: h () house of the key OR, exit

KOTOROG O S: HODS M sbroSy

trigger,; h-g l-f 1;: ;; ;; р ;; л1Ы; -; input c; even- i p i

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length

.lO: trolling: -: oh after.to..a gel); soy; ine11 with. ; lev.g; k) 1; 1, um input zanr-gh e: erato:) and tgp-tozk-1s,

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Claims (1)

SUMMARY OF THE INVENTION A signature analyzer comprising a clock, a counter, a shift register, a trigger, and an OR element, the group of information outputs of the shift register being a group of information outputs of the analyzer, for the purpose and This analysis, taking into account the real distribution of possible errors in the output sequences of controlled discrete devices, the information input of the analyzer is connected to the counting input of the trigger, the output of which is connected to by the input of the sequential recording of the shift register, the reset input of which is connected to the first input of the элемента .PI element and is the setup input of the analyzer, the start control input is connected to the start of the getter. clock pulses output kstsrogo siphrovhodom schezchika to-th output (2 length of separately gu emoy poγ, πγ.ποιpa ι Vai modes for the clock is connected to the bit kontrolisnorachi _s where r = _{_log;!} rJ core ι gsenta gj "vn.. spans;, two each) connected to the shift register and lemont xd: d. output with reset input d main output count '· k] next turn on) sit by the input of forbidden pulses _e