SU955162A1 - Increment signal transmission device - Google Patents

Description

one

The invention relates to communication and telemetry techniques and can be used in the transmission of photo-television signals.

A device for transmitting increments of digital signals is known, which comprises a clock generator, a converter. Analog — a digit, an adder, a sign analyzer, a driver, a matrix switch, a reversible counter and a logic switch. The device generates a sequence of delta signals O and 1, the weights of which, with the same quality of the packages, are assumed to be equal to twice the weights of the previous packages. If during the development of the increment of the initial digital signal the sum of the weights of the delta signals after summing the Gth weight parcel exceeds the increment value, then the sign of the (+1) parcel is reversed, and its weight is reduced twice as compared to the weight of the previous parcel. one.

The drawback of the device is the relatively large variance of the overload error. This is due to the oscillatory nature of testing the jump of the original digital signal.

Claims (2)

The closest in technical essence to the proposed invention is a device for transmitting signals of increments, containing an analogue to digital converter, the input of which is connected to the device input, a sign analyzer and; differences whose inputs are connected respectively to the analog-to-digit converter, the adder and the first output of the matrix switch, the second and third outputs of which are connected to the corresponding inputs of the adder, the first output of the clock generator is connected to the synchronization outputs of the matrix switch and the signal generator, the author of the generator output is the analogue synchronizing inputs of the analogue are the digit of the logical switch and the analyzer of the sign and the difference, the outputs of which are connected to the corresponding conductive switch logic inputs, the first outputs of which are connected to respective inputs of the matrix switch, vyho second rows are connected to a coding input unit, which outputs are connected to inputs of the signal shaper whose output is connected to the output device. In this device, by comparing the digital Lee signal, () and the reconstructed digital signal A0 (t;), the difference l A (t) is calculated and the sign of the difference is determined. According to the analyzer's signals, de ta-signals are generated. In this case, the weight of the next parcel doubles if the difference is equal to or exceeds the value of the doubled weight of the previous parcel and becomes equal to the weight of the previous parcel, if the difference is less than twice the weight value of the previous parcel G2. The disadvantage of the device is the need to ensure tight synchronization with the frequency of the disk | The initial digital signal is used for the underlying transmission, since the input from the clock point of the delta transmission has a weight equal to 1. The purpose of the invention is to increase the accuracy by adapting to the character of the input digital signal and at the same time ensuring low dispersion of the overload error. . The goal is achieved by the fact that the device for transmitting incremental signals containing an analog-to-digital converter, the first input of which is connected to the input of the device, the output - to the first input of the block determining the sign of the difference of signals, the outputs of which are connected to the first inputs of the logic switch, generator sync pulses, the output of which is connected to the second inputs of the analog-digital converter and the difference sign determining unit and the first input of the adder, the second inputs and the output of the adder are connected respectively but with the switch outputs and the third input of the signal difference detection unit and the output driver, the COD of which is connected to the device output, a reversible counter and a delay element are inputted, the input of which is connected to the output of the clock generator, the output of the delay element is connected to the first inputs of the switch, reversible counter, the third input of the adder and the second input of the logic switch, the first outputs of which are connected to the first inputs of the output signal generator, the second output - with union of the second input of the output pulses and a reversible counter, the third switch outputs are connected to logic inputs of the third down counter, the first and second outputs which are respectively connected to second inputs, the switch and with the third input of the output signals. FIG. 1 shows a structural diagram of the proposed device; FIG. 2 - time diagrams that show his work. The device consists of an analog-digital converter 1, a sign definition unit 2, an adder 3, a matrix switch C, a driver 5 output signals. Generator 6 clock pulses, logs of the switch 7} of the delay element 8 and the reversible counter 9 The device operates as follows. The digital signals Lc (11-) generated by the transducer I are fed to block 2 for determining the sign of the difference, where the reconstructed digital signal LIR (tO) comes from adder 3. Block 2 calculates the difference -iA (-t.) Yt, bX, (- | ), where T / 2 is half the clock interval by which the pulse sequences are shifted (Fig. 2.1; 2.2; 2.3). Block 2 produces six types of signals: +, -, O, V,, /. Signals +, - and O indicate the sign lA. (t). The signal b shows that lL (t) 7 / 2di-, where is the weight of the previous binary premise. Si1nal means that the value (t;) 2y.-. The signal indicates that L (tf): uj.,. In the logic switch 7, a series of gates + is formed from these signals (Fig. 2), -. (Fig. 2.5),. (Fig. 2.6), O or Fig. 2.7g V (Fig. 2.8), +, (Fig. 2.9) / (Fig. 2.11). Using the gate O or (Fig. 2.7), a reset pulse is generated for the reversible counter 9 and pauses are formed in the output signal of the driver 5 (Fig. 2.7). With the aid of gates +7, and and pulses (Fig. 2.3), in the reversible counter 9, pulsing pulses (Fig. 2.10) and subtraction (Fig. 2.12) are formed. Gates + and - (Fig. 2.13 and 2.1) are used to form the output signals in the shaper 5 at the input of which from the counter 9 pulses are added (Fig. 2.10) and subtraction (Fig. 2.12). The output signal of the device is shown in FIG. 2.15, and the code is shown in FIG. 2.16. Consider the operation of the device, for example, the input signal Lc (), shown in FIG. 2.1 At clock points (Fig. 2.2), Л L (ti) is calculated and the signals of block 2 produced above are generated. According to them, gates + 7 /,, О or gates + and - are formed in switch 7. In the reversible counter 9, either the summation of the input pulses (Fig. 6.3) or the subtraction or preservation of the last number occurs (when the O or strobe is applied). The output potentials of the estimator trigger cells 9 are converted into switching gates generated by the switch k. The gates of switch k send the corresponding inputs of the RS flip-flops of the adder 3. With the input of adder 3 open, if it was previously in the state O or 1, a pulse arrives at the input, the trigger goes to state 1 or O and in the adder 3 the number increases by 2. Simultaneously with the change in the number in the adder 3, a parcel weighing +2 is transmitted to the communication channel. In the proposed device, after a pause, the package has a weight of 2 °, i.e. the end of the pause is sync. The pause corresponds to dL (tQ) 0 and uX (t |) .d, i.e. as the recovered signal approaches 0, (ti) to i, the initial Lc (t) weight. summed increments are made equal to 1. In addition, the adopted algorithm provides less error variance than in the prototype due to the exclusion of the oscillatory nature of the reconstructed signal. The device provides a small error dispersion both in comparison with a system in which conventional delta modulation is used, and with a system that adapts to the message. The system operation algorithm yields a small variance for both fast and slowly changing signals, i.e. the reliability of the device is enhanced. t The device can be used in the transmission of telemetry information, in the transmission of voice signals, in phototelegraphy and television, as well as in data transmission. Apparatus of the Invention An incremental signal transmission device comprising an analog-to-digital converter, the first input of which is connected to the device input, the output is connected to the first input of a signal difference detection unit, the outputs of which are connected to the first inputs of a logic switch, a sync pulse generator whose output is connected to the second inputs analog-to-digital converter and a unit for determining the sign of the difference and the first input of the adder, the second inputs and the output of the adder are connected respectively to the outputs of the the mutator and the third input of the signal difference detection unit and the output driver, the output of which is connected to the output of the device, characterized in that, in order to increase the reliability of the device, a reversible counter and a delay element, the input of which is connected to the clock generator output, are entered into it The delay element is connected to the first inputs of the switch, the reversible counter, the third input sum TQpa and the second input of the logic switch, the first outputs of which are connected to the first input the former, with the combined second inputs of the output pulse generator and the reversible counter, the third outputs of the logic switch are connected to the third inputs of the reversible counter, the first and second outputs of which are connected respectively 79 but with the second inputs of the switch and with third inputs shaper output signals. Sources of information taken into account during the examination 55162 1. USSR author's certificate No., cl. G 08 C 19/28, 1975. 2.Certificate of the USSR N 601736, cl. G 08 C 19/28, 1976 (prototype). Fig 1 , ft I t I j I II t I I I I 1 M 1 t M t I I 1 | l t 1 I I t I I M, t ft M t t 1 M I I JtU I M J I rt t t i lit t 1 I i „t one A. tf. te f ifn m rsn w i I ha t.7 П П П 1 I П Jel -P P t.i .f GTAP NSG frn Caatftnat I I III W M YoahDKKSH KGKD m T .g .