SU1332542A2 - Device for dividing directions of transmission in duplex communication systems - Google Patents

Abstract

The invention relates to telecommunications technology and provides improved noise immunity. The device contains block 1 srlasovany, switches 2 and 15, DAC 3, 11, 28, ADC 4, shaper 5 code combinations, chip unit 6, 10, 16, 18, r-r 7 control pulses, subtractors 8, 14 , 17, adders 9 and 19, a number-forming unit 12, a shift register 13, an adaptive delay unit 20 consisting of flip-flops 21 and 25, an And 22 slot, counters 23 and 26, a threshold unit 24 and a random access memory unit 27, control unit 29. 5 3 .p. f-ly, beat. g (L with with 1CHE SL to N .t

Description

The invention relates to telecommunications technology, can be used in data transmission systems on channels

communication to separate directions again.

problem, and is an improvement to the device described in ed. St. No. 1133675.

The purpose of the invention is to increase the noise immunity .10

FIG. 1 shows the structural electrical circuit of the proposed device; in fig. 2 - embodiment of the matching unit; in fig. 3 shows an embodiment of form-15 body code combinations; in fig. 4 — embodiment of the control unit; in fig. 5 shows an embodiment of the number-forming block; in fig. 6 - epures

The operation of the device can be divided into the process of preliminary adaptation for the parameters of the communication channel and the process of duplex information transfer.

The pre-adaptation process is as follows.

From the control output (data terminal equipment (DTE) is not shown at time C, a logical zero arrives (Fig. 6o). This signal connects (Fig. 1) the output of the driver 5 through the first switch 2 to the input of the first D / A converter 3 (Fig. ), and also flushed the second

voltages that determine the operation of the device; 20 memory block 10 and a meter 36 in the block

etva.

A device for dividing transmission directions in duplex communication systems contains (FIG. 1) matching unit 1, the first one fytatopop 2, first digital-to-analog converter 3, analog-to-digital converter 4, driver 5 code combinations first block 6 of memory, generator 7

control pulses, the first subtraction (Fig. 6a). At the first output of the decoder

tele 8, first adder 9, second memory block 10, second digital-to-analog converter 11, number generation block 12, shift register 13, second subtractor 14, second, switch 15, third memory block 16, third subtractor 17, fourth memory block 18 ty, second adder 19, adaptive

a delay unit 20 consisting of a first trigger 21, an element 22, a first counter 23, a threshold block 24, a second trigger 25, a second counter 26, and a random access memory 27, a third digital-analog converter 28, a control block 29.

The matching unit 1 comprises (Fig. 2) a delay line 30, a permanent storage unit 31 and an adder 32 modulo two.

The shaper 5 of the code combinations Q digital combinations for the preliminary contains (Fig. 3) counter 33, stationary training of the entire device into the storage unit 34 and the prohibition element 35.

The control unit 29 comprises (FIG. 4) a counter 36, a decoder 37 and a prohibition element 38.

The block 12 of the formation of numbers contains (Fig. 5) the block 39 of the formation of significant moments, the measuring

55

communication channel parameters. In the permanent storage unit 34 (FIG. 3), the allowed digital combinations are stored at addresses from zero to 2 (r - -discharge of counter 33). The number of digital combinations used (z) depends on the use of the first, second and third digital-to-digital counter 40, the buffer memory block 41 and the limiting amplifier 42.

The device operates as follows: the device can be divided into a process of preliminary adaptation to the parameters of the communication channel and the process of duplex information transfer.

The pre-adaptation process is as follows.

From the control output (not shown) of the data terminal equipment (DTE) at the time C, a logical zero arrives (Fig. 6o). This signal connects (Fig. 1) the output of the driver 5 through the first switch 2 to the input of the first D / A converter 3 (Fig. 6), and also zeroes the second

29 control (FIG. 4). When resetting the counter 36 in the control block 29, the prohibition signal is removed from the second input of the prohibition element 38. The clock pulses pass through the prohibition element 38 (Fig. 6i), but the counter 36 remains in the zero (initial) state, since its R-input from the DCO receives a nulling potential

five

0

five

of the torus 37 in the control unit 29 a short pulse is formed (Fig. 6b), which resets the counter 33 in the former 5 (Fig. 3) to the zero state. When the counter 33 is reset, the blocking signal is removed by the second input of the prohibition element 35, thereby allowing the passage of clock pulses from the generator 7 output to the clock input of the counter 33 (Fig. 6).

After the arrival of a short pulse from the first output of the control block 29 (Fig. 6c), the clock pulses, having passed the prohibition element 35, arrive at the clock input of the counter

33, changing the state of the latter (Fig.6). Counter 33 changes addresses in a persistent storage unit (ROM)

34 in which are stored the necessary

digital combinations for pre-learning the entire device under

communication channel parameters. In the permanent storage unit 34 (FIG. 3), the allowed digital combinations are stored at addresses from zero to 2 (r - -discharge of counter 33). The number of digital combinations used (z) depends on the use of the first, second and third digital-analogue converters 3, 11.28, and analog-digital converter 4 as Z 2. At ten bits, the number of binary combinations is 1024 (Fig. 6d, e ).

Thus, the counter 33 enumerates the addresses of the persistent storage unit FOR, the input digital combinations corresponding to U are supplied to the input of the first digital-to-step converter 3, which correspond to U. (Кл t), which are converted to the corresponding analog voltages Uj (t). It should be noted that, depending on the connected communication channel, the values of U (t) can vary widely. FIG. 6 J on the time interval t -t, the given digital combinations are shown and j (K 4t), which are then converted into binary combinations by an anapographic converter 4. In this case, the value Uo (K / lt) corresponds to Up (t) at the output of the first digital-to-analog converter 3, and Uj (K jt) at the output of the analog-to-digital converter ADC 4. Similarly, you can record:

and / to 4t) -) - and (to at)

and, (K t) - U, (t) - and, (K at)

u-CKdt) (t) u.CKdt) (1)

The values of and, (to it), which are the responses of the input of the communication channel to the corresponding digital combinations, are recorded in the first memory block 6 in accordance with the compression (1), i.e. 40, the cell with the address t) records the response Uo (K at), etc.

After forming the last allowed digital digital combination 45 and (K 4t), a short pulse (Fig. 6k) is generated at the third output of the permanent storage unit 34, which is fed to the DTE. On this signal, the supply of a logical-gQ-th zero (Fig. 2a) from the DTE, the reset of the second memory block 10 and the counter 36 in the control block 29 is stopped. However, at the end of the control signal from the DTE output (Fig. 6), the first switch 2 gg remains in the same state (Fig. 6), connecting the output of the driver 5 to the input of the first D / A converter. It should be noted that

in the process of preliminary adaptation, the signals of the opposite side, according to the recommendation of the gastrointestinal tract, should be absent.

Starting from the time t to the time tj (Fig. 6), the counter 33 in the imaging unit 5 changes its state from 2 to 2 (). These addresses in the permanent storage unit 34 recorded samples of the probing signal C (K Jt), where 1m is the frequency of the probing signal necessary to determine a smooth delay; t - smooth delay. Smooth delay is the time between the beginning of a signal transmission and the moment of appearance at the point of transmission of the first channel echo response to the transmitted signal. Sounding signal is

W, UpU) (w, K A t).

(2)

The sounding signal and. (K At) is converted by the first digital-to-analog converter 3 to the analog signal U ((t), which is fed to the communication channel and simultaneously to the analog-to-digital converter 4, where it is quantized in terms of the form I (К & t). The signals and, (to dt) are fed to one of the inputs of the first subtractor 8 and to the input of the first memory block 6. Since the probing signal U, (K dt) is composed of allowed samples U, - (K ijt), the responses on which are written as binary combinations in the first block of 6 memory, then when transferring one of the allowed levels, to example U (, (Kdt), at the output of the first subtractor 8, we will have

L / K dt) Uo (Kp, Jt) -lJe (K, 4t), (3)

where U (, (K at) and UO (K, Jt) are the responses of the communication channel to the same digital combination U (, (K l t) at different () and (KJ jt) points in time. The situation is similar in the transmission of any another combination of U ((K at).

Thus, the probing signal and to, (K ut) does not pass in the direction of its own receiver (not shown).

The situation is different with the appearance of an echo signal which, after a certain period of time, appears at the output of the analog-digital converter 4. According to theoretical and experimental studies, this

the length of time, depending on the length of the tone frequency channel, can vary from almost zero to 500 m / s (for satellite communication channels).

So, after a clock interval at the input of analog-digital converter 4, an echo signal appears, which is due to the sounding signal Uw, (t).

Then at its output we will have the sum of two components: the probing signal itself U, (K 4C) and the echo signal / -

At the output of the first subtractor 8, when transmitting any allowed level, for example, again Uo (K 4t), we will have

Lo () Uu., (K, it) + and, Hosh / "(Kn, 4t) -UCJ / K, jt))," (K,., Dt). (4)

Mtl

Since in the time interval t +

g

the second memory block 10 was zero, the signal at the output of the first adder 9 in this case will be equal to

M, (Kn., Jt) U5, o (j, (Kf, +, dt) + O U ,,, / K ,, 4t). (5)

Signal U, vn O). (TO

g

that

j, .t, At) is written to memory at

 echo

in the second block 10 UO (K dt).

The situation is similar when the shaper of 3 other digital samples of the probing signal is transmitted by the former ()

Indeed, if the driver 5 again generates the value UQ (K 4t), then at the output of the first subtractor 8 we will have

LO (K

h +

dt)

and 9X0 w (to n + 2 at)

 Uo (, t) - UjxoWiCKn i lt) - - UO (K + ut) Ua, ou., ()).,

Jt)

(6)

As can be seen from formula (6), at the output of the first subtractor 8, when compensating for signals from its own transmitter, the received signal from the communication channel is represented by the difference of the received signal in the two adjacent clock intervals c. With the help of the first adder 9 and the second memory block 10, this modulation is eliminated.

Indeed, the output of the first adder 9 will be.

MO (K,

.; jt) L (K ,,,, it) +

Mo (K, Jt)

) to and.

(TO.

It). (7)

ten

15

20

25

thirty

The value of the echo signal Uj d (K dt)

recorded at the same address

Ug (K At) in the second block of memory, etc.

Thus, when the probing signal U (j (K and t)) is formed by the probe shaper at the output of the first adder 9. However, all the echo signals that pass through the differential system of the PM channel pass through this direction separation device .

These digital samples echoes and 3x0 c; (K 4 t) are converted into analogue form Uanouj - ° a second digital-analog converter 11 and are fed to the input of the number-forming unit 12.

The number generation unit 12 (Fig. 3) amplifies and limits the signal UjKouj t) in the limiter amplifier 42. Further, in the significant moment formation unit 39, zero-crossing signal Uj ouj / t) is marked by short pulses. In the meter 40, the time is measured between the adjacent 1 and (1 + 1) half periods of the hour.

0

0

five

tots U) probing signal

and 9KO U), (t).

The measurement result in the form of a binary number (-A () is recorded in block 41 of the buffer memory with the arrival of the next (1 + 1) short pulse. Thus, binary numbers (-A,) will appear alternately at the output of the number-forming unit 12 characterizing the duration of the half-periods of the signal U echoes s (t).

The numbers (-A-) begin to pass on the 5th first input of the second subtractor 14 and at the same time through the shift register 13 to the second input of the second subtractor 14. Since at time tj (Fig. 6) a short-term tamping potential was fed to the first input of the shift register 13 , then until the shift register 13 is completely filled, the output of the second subtractor 14 will be the duration of the half-periods -A ,. After filling in the shift register 13, the difference value (A.) appears at the output of the second subtractor 14, where the K value characterizes the length of the shift register 13.

Since from the time t to t the third memory block 16 is reset (6), the output of the second subtractor 14 through the second switch 15 and the third calculator, Uy (t) does not pass towards its own receiver. The output of the first switch 2 will only be present echoes U, oj (t),

ten

The reader 17 is connected to 5 which are caused by the signal Tsc, (t), the input of the second adder 19. The signal Uo (t), passed the 12for unit. At the output of the second subtracter of numbers, the number (-A) is converted, which numbers (+ V), similarly obtained, characterizes the duration of the first half-period of the signal frequency (t) This number (-A) passes through the second subtractor 14, the second switch 15 and the third subtractor 17 are fed to the input of the second adder 19. Since the fourth block 18 memory from the time t to t was reset (fig.bz), then the output The second adder 19 will have a number (-A). With the arrival (-AJ) at the output of the second adder 19, we have - (A A), etc.

After filling in the shift register 13, the output of the second adder 19 will be

to

20

earlier numbers (-A,), which characterized the signal U, xoto (t). Thus, as soon as the signal U ,, d j (t) is received from the communication channel, this means that the smooth delay has ended. For the convenience of implementing an adaptive delay unit 20, in which the magnitude of the smooth delay is fixed, choose lAj (B,. |.

To this end, the clock input of the measuring counter 33 from the output of the generator 7 serves the frequency defined by the expression

t + 1 f -. . . (.eleven)

t - (A ... + A) -X A..8)

25

2U ..

one

2co

fii

After (K + 1) half period we will have

k11 + 1

 -11 A - A, - (- A., -Z A; (9)

)

thirty

14

After (K + n) half-periods we will have

K. + P

-LA. . (ten)

i h

Thus, starting from the moment

(

where m is the counter size 35; u) j- frequencies of the probing signals} (t) and U, (t), respectively.

Upon receipt of numbers + B, characterizing the duration of the half-cycles of the frequency Wj of the signal Ui (t), the input of the second adder 19 at its output after a certain time, called the angularisation time, a signal equal to

fctm

T f I () t.

t, and up to t,

the second adder 19, together with the fourth memory block 18, performs the function of a sliding sum-torus 40. At time t, the imaging unit 5 begins to generate the second probing signal and (K 4.t). For this purpose, clock pulses, passage through prohibition element 35 translate counter 33 in imaging unit 5 into f I () t.

The time between the beginning of the transmission of the signal UujjCt) and the appearance of the signal and, 5y (t) of the transmitted echo path of the connected communication channel, characterizes the magnitude of the smooth delay. To measure it, the first trigger 21 serves

 - -. --- .- element 22 and the first counter 23 in

2 (where g is the bit size of the adaptive delay unit 20 (Fig. 1). ZZH chic. In a permanent memory. When forming a Uu (K dt) signal 34 by addresses, starting with 2 driver 5 at the second output under 2 , a digital pulse of the second one is recorded; the last is a short pulse of the sounding signal Uu (K Jt), (FIG. 6), which sets the first constituting sinusoid with a new trigger 21 to one with the following frequency u) i. ( Fig. 6H), and the first counter 23, with the Pickup signal U (t) is instinctively set to the original

.. gg growth (fig.br). First trigger 21

forcibly unlocks the element, AND 22 (fig.bp), thereby the clock pulses from the output of the generator 7 are passed to the input of the first counter 23, the coet is connected to the communication channel and at the same time to the analog-to-digital converter 4. As U (t) is also composed from digital samples U (K.dt), the responses to which are in the first block 6

memory, then Uy (t) does not go towards its own receiver. The output of the first switch 2 will only be present echoes U, oj (t),

which are caused by the signal CC, (t), the Signal U о (t), passed the block 12for

world number is converted to numbers (+ V.), similarly obtained

earlier numbers (-A,), which characterized the signal U, xoto (t). Thus, as soon as the signal U ,, d j (t) is received from the communication channel, this means that the smooth delay has ended. For the convenience of implementing an adaptive delay unit 20, in which the magnitude of the smooth delay is fixed, choose lAj (B,. |.

To this end, the clock input of the measuring counter 33 from the output of the generator 7 serves the frequency defined by the expression

t + 1 f -. . . (.eleven)

2U ..

one

2co

where m is the counter size 35; u) j- frequencies of the probing signals} (t) and U, (t), respectively.

Upon receipt of numbers + B, characterizing the duration of the half cycles of the frequency Wj of the signal Ui (t), the input of the second adder 19 at its output after a certain time, called the angularisation time, results in a signal equal to

fctm

AT,. (12)

T f I () t.

The time between the start of the transmission of the signal UujjCt) and the appearance of the signal and, 5y (t) of the transmitted echo path of the connected communication channel, the characteristics and begins to change its state until the signal T (K + ha), which returns the first trigger 21 to the initial state (Fig. 6) and closes the AND 22 element. It should be noted that the counter 23 is executed with a preset in which the number equal to half the length of the shift register 13 is fixed at the first moment K / 2. The binary number, which is recorded in the counter 23, characterizes the smooth delay of the given communication channel.

At time t, the counter 33 reaches the value 2. Thereafter, the prohibition element 35 is closed, and the driver 5 stops its operation.

At time t, the separation device begins to be trained for echoes.

For this purpose, the signal from the second output of the second counter 26 will reach

the progress of control block 29 connects the output of the first adder 9 through the second switch 15 to the input of the third memory block 16 and to one of the inputs of the third subtractor 17 (Fig. 6k).

Starting from the moment t to the moment t, the fourth block of the memory block 18 (Fig.bx) is reset by the signal from the third output of the control block 29.

A short pulse from the fourth output of control block 29 (Fig. 1 at time t) returns the first switch. Since the output of the second counter 26 is connected to the address inputs of the on-line storage unit 27, then the protor 2 returns to its original state. Thus, if the input of the adaptive output of the DTE begins to receive a random binary signal a. (Fig. 6c), which in block 1 with the help of adder 32 modulo two and l SRI delay 30 40 (2) perekodiruets otnositelizvodits symbols in a delay. smoothly

A generic delay unit 20 appears the information symbol a. at time t

appears at t + t ..,

1 ch. in

(Fig.6 g), then at its output this symbol a I (Fig.6 v).

ny signal according to the following law (6): a a- 0 a. , (13)

where a. and a. - respectively, the recoded and non-recoded binary symbols to be transmitted .50 In accordance with the value of the recoded signal, the corresponding digital samples are stored in the permanent storage unit 31 and, - (Kdt), the order of which the corresponding signals pass through; - the amplitude, frequency, or phase out of the communication channel. Since echo modulation. It should be noted that

   ° h give over the communication channel (fig. 6t), each

from the transmitted characters a. consists of a set of expanded digital combinations U; (K ut).

As shown above, the transmitted signals U (t) from the output of the first D / A converter 3 do not pass to the input of their own receiver. To a receiving device (not shown)

the signals are returned from the communication channel through a smooth delay time, then the set of transmitted symbols

for each recoded character, a corresponds to a certain aggregate.

ten

.

the number of digital samples U, - (К / i t), the responses of the CS to which are recorded in the first block 6 of the memory.

The transcoded characters al are fed to adaptive delay block 20, which is supposed to delay them exactly by the amount of smooth delay. As shown above, the value of the smooth delay in the form of a binary number stores 10 seconds in the first counter 23.

Let the second counter 26 and the second trigger 25 be in the zero state. The second counter 26, under the action of clock pulses from the output of generator 15, begins to change its state. The threshold unit 24 compares the state of the second counter 26 with the smooth delay stored in the first counter 23. As soon as the values of the smooth delay are present, a logical unit appears at the output of the threshold unit 24, which is fixed in the second trigger 25. The signal from the output of the second trigger 25 trigger 25 zeroes the second counter 26, and the last operation cycle repeats. Thus, the period of operation of the second counter 26 is determined by the value of the smooth delay,

which we denote by t. (Fig.6).

Ch. 5ad

Since the output of the second counter 26 is connected to the address inputs of the operative storage unit 27, then about the smooth delay value, Thus, if

 the value of the smooth delay, Thus, if the input

the delay of characters a is exhausted. smooth

 the value of the smooth delay, Thus, if the input adap

A generic delay unit 20 appears the information symbol a. at time t

 the value of the smooth delay, Thus, if the input

appears at t + t ..,

1 ch. in

(Fig.6 g), then at its output this symbol a I (Fig.6 v).

Let, at the input of the persistent storage unit 31, the binary symbols a,

but

which need to be passed through lid signals that come from the communication channel. Since the echo

   ° h give over the communication channel (fig. 6t), each

from the transmitted characters a. consists of a set of expanded digital combinations U; (K ut).

As shown above, the transmitted signals U (t) from the output of the first D / A converter 3 do not pass to the input of their own receiver. To a receiving device (not shown)

Lid signals that are received from the communication channel pass. Since the echo

the signals are returned from the communication channel through a smooth delay time, then the set of transmitted symbols

II

g

which are delayed by the smooth delay time in adaptive delay unit 20, the communication channel responds with a corresponding echo and, 0 (t).

Similarly, on the combination a, a,. .., and the communication channel responds with an echo signal and (t), etc. If the set of symbols aj to submit as addresses efO, l to the third 16 and fourth 18 memory blocks in the third memory block 16 from time t to tj will be recorded samples of the echo signals Ujxo. (t). At the same time, for each binary digital combination of symbols aJ, at the output of the adaptive delay block 20, the communication channel gives only its response Ujvoj (t). This makes it possible to compensate the echo signals with the help of the third memory block 16 and the third subtractor 17, and using the second adder 19 and the fourth memory block 18 to restore the shape reduces the element

12 38

the ban

ten

15

20

control unit 29 itself finishes its work.

Since the samples U- (K jt) and Ujxo (4t) recorded in the first 6 and third 16 memory blocks depend on the connected communication channel, this device is adaptive and allows adjustment to any two-wire communication channel parameters.

The process of dividing transmission directions in duplex communication systems can be multiplied as follows.

Let the binary symbol a -I- t be the transcoded binary symbol at the input (i + t ,.) time interval, where tr, O3Ha4aeT is the smooth delay value. At its output, the symbol a - t g J corresponds to a set of digital binary combinations, for example, U (, (K 4t), U, (K at), ....

mated signal. Echo-sig-25 compensation, wherein these digital combinations are input to the first digital-to-analogue converter 3 sequentially one after the other. Each of the transmitted symbols Uj (K At) is compensated using the first memory block 6 and the first subtractor 8, all signals that are are received from a two-wire communication channel; the output of the first vpr 4 is found to be modulated according to the law of transmitted data (formulas 1–7); the shape of the received signals is reconstructed using the first adder 9 and the second memory unit 10 stepping on their two-wire communication channel. After learning, the second switch 15 switches the output of the first adder 8 to the input of the third memory block 16 and the third subtractor 17.

thirty

The wadding is done in the same way as the transmitter signals that penetrate directly to the input of their own receiver.

Thus, the first memory block 6 and the first subtracter 8 are a kind of filter plug for the signals of the own transmitter penetrating the receiver input. In this case, the first adder 9 and the second memory block 10 allow to restore the shape of the received signal and the echo signals and to skip them without distortion from the communication link (the echo signals and the received signal of the opposite side). I

The third memory block 16 and the third

subtractor 17 are. filter plug for echoes. In this case, the second adder 19 and the fourth memory block 18 allow the received signal to be skipped without distortion.

At the moment t, the training of the device under the parameters of the communication channel is completed. At the same time, in the first memory block 6, the input channel responses U are stored: (K 4t) on the digital binary combinations Uj (K jt), and the third memory block 16 stores the channel responses and, o (K dt). In the adaptive blocking of characters and from the output of adaptive40

45

50

Binnings are fed to the input of the first digital-to-analog converter 3 sequentially one after another. Each of the transmitted symbols Uj (K At) is copied with the first memory block 6 and the first subtractor 8, all the signals that come from the two-wire communication channel are The output of the first vr4itel 8 is modulated according to the law of transmitted data (formulas 1-7). The first adder 9 and the second memory block 10 restore the form of the received signals coming from their two-wire communication channel. After learning, the second switch 15 switches the output of the first adder 8 to the input of the third memory block 16 and the third subtractor 17.

Adaptive delay unit 20 at its output issues delayed transmitted symbols a., Which are addresses in the third 16 and fourth 18 memory blocks. With the help of the third memory block 16 and the third subtractor 17, the echo signals U5 are compensated (o- (t) while the received signal is modulated again, the smooth delay value is stored by the law of the delay track 20). 29 controlling the last clock from the fifth output of the decoder 37 (FIG. 4)

whom block 20 delay. With the help of the second adder 19 and the fourth memory block 18, the form of the received signal y (K) is restored,

element

12 38

the ban

control unit 29 itself finishes its work.

Since the samples U- (K jt) and Ujxo (4t) recorded in the first 6 and third 16 memory blocks depend on the connected communication channel, this device is adaptive and allows adjustment to any two-wire communication channel parameters.

The process of dividing transmission directions in duplex communication systems can be multiplied as follows.

Let the binary symbol a -I- t be the transcoded binary symbol at the input (i + t ,.) time interval, where tr, O3Ha4aeT is the smooth delay value. At its output, the symbol a - t g J corresponds to a set of digital binary combinations, for example, U (, (K 4t), U, (K at), ....

   the data is digital and the data is digital com

Vani characters and with adaptive output

The binaries are fed to the input of the first digital-to-analog converter 3 sequentially one after another. Each of the transmitted symbols Uj (K At) is compensated by the first memory block 6 and the first subtractor 8, all the signals that come from the two-wire communication channel are output The first vpr 8 appears to be modulated according to the law of transmitted data (formulas 1-7). The first adder 9 and the second memory block 10 restore the form of the received signals coming from their two-wire communication channel. After learning, the second switch 15 switches the output of the first adder 8 to the input of the third memory block 16 and the third subtractor 17.

The adaptive delay unit 20 at its output issues the delayed transmitted symbols a., Which are addresses in the third 16 and fourth 18 memory blocks. Using the third memory block 16 and the third subtractor 17, the echoing of characters is compensated and from the output of the adaptive signals U5, (o- (t), the received signal is modulated again, already according to the law of following the characters and from the output of the adaptive delay unit 20). Using the second adder 19 and the fourth memory block 18, the received waveform y (K) is restored, and

13133

using the third digital-to-analog converter 28, it is converted to analog REED y (t) and output to

receiving device (not shown).

Thus, in one frequency band, two transmission directions with coinciding spectra in the presence of echo signals are separated.

Claims (5)

1. A device for dividing transmission directions in duplex communication systems according to auth. No. 1133675, characterized in that, in order to increase the noise immunity, an adaptive delay unit, third and fourth memory blocks, a third digital-to-analog converter, a control unit and a serially connected number generation unit, a shift register, a second subtractor, the second input of which is connected to the output of the block are inserted numbering, the second switch, to the control input of which the first output of the control unit is connected, the third subtractor, to the second input of which the output of the third memory block is connected, and the second sum p, the output of which is connected to the input of the third digital-to-analog converter and to the first signal input of the fourth memory block, the second signal input of which is connected to the second signal input of the third memory block, to the first signal input of which the output of the second switch is connected, with the second register input shift, with the first input of the number-forming unit, to the second input of which the output of the second digital-to-analog converter is connected, with the output of the control pulse generator, which is connected to the first to the input of the adaptive delay unit, and with the first input of the control unit, the first, second, third and fourth outputs of which are connected respectively to the first control input of the third memory block, the second control input which is connected to the output of the adaptive delay unit, to the first control the input of the fourth memory block, the output of which is connected to the second input of the second adder and the second signal input of the adaptive delay unit, to the second control 0 5 0 5 0 5 0 5 Q c the main input of the forward switch and to the control input of the code generator, the second output of which is connected to the control input of the adaptive delay unit, the information input and output of which are connected respectively to the second output of the matching unit and the second control input of the fourth memory block, the information input of the second switch is connected to the information input of the second memory block, the installation input of which is connected to the second input of the up-block. gov. 2. A device according to Claim 1, characterized in that the adaptive delay unit comprises a first trigger connected in series, an element I, a first counter, a threshold unit, a second trigger, a second counter and an operational storage unit, the second input of which is connected to the second inputs of the second trigger, element And the second counter and is the first signal input of the adaptive delay unit, the second signal input of which is the first input of the first trigger, the second input of which is connected to the second input of the first counter and is control exhibiting an input of the adaptive delay unit, data input and output of which are respectively the third input and an output random access memory unit, the first input coupled to the second input of the threshold unit. 3. The device according to claim 1, characterized in that the matching unit contains a delay line and a series-connected adder modulo two and a persistent storage unit, the second input of which is connected to the first input of the delay line, the second input and output of which are connected respectively to the output and to the first input of the modulo two, the second input of which is an information input of the matching unit, the control input and the first and second outputs of which are, respectively, the second input and output of the persistent storage unit and the output of the modulo-two adder. 4. The device according to claim 1, characterized in that the driver code combinations contains 15 Consequently, the prohibit element, the counter and the persistent storage unit, the outputs of which are the outputs of the shaper code generator, whose input is the first input of the prohibition element, to the second input of which is connected the second output of the counter, the second input of which is the control combination shaper input . 5. A device according to claim 1, characterized in that the control unit comprises a prohibition element connected in series, a counter and a decoder, one output of which is connected to the first input of the prohibition element, the second input of which and the second input of the counter are respectively 2 but the second and first inputs of the control unit, the outputs of which are the other outputs of the decoder. 6, The apparatus of claim 1, wherein the number generation unit comprises a series-connected limiter, a value generation unit, a measuring counter and a buffer memory block, the output of which is the output of the number generation unit, the first and second inputs of which are respectively, the second input of the measuring counter, the first input of which is connected to the second input of the buffer memory unit, and the input of the amplifier-limiter.