SU942132A1 - Buffer storage - Google Patents

Description

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The invention relates to computing | i can be used in the construction of storage devices. Digital universal / spalialized machines.,

A memory device is known which consists of a control block, a cipher cipher of an acres code, elements AND, shapers of GOKES for combining and recording, for-. worlds of prohibitory currents, accumulator with additional charge, playback amplifiers, gating amplifiers, number register and trigger Il.

However, the device does not provide reliable operation, when the write and read modes are inconsistent between J5.

It is also known a buffer storage device (BZU), consisting of four-bit shift registers, accumulator-20 bodies, input device, output device, AND elements, synchronization unit, OR elements, counter and generator of single pulses 12 J.

The main disadvantage of this device is the low fast action and long waiting time information due to the sequential action of the RAM.

The closest to the proposed teasa entity is a device containing a magnetic pin on the cores with address and discharge settings, interrogation and output dialing, radial and address counters, recording and interrogation generators, an aapapie control circuit, and an accumulator and eadervkhi circuits An optional memory block on the elements with a central storage without destroying information, a reset generator and a polling switch. Shi; Readings (records) of the memory elements of the additional memory block are connected in series with the corresponding pins of the magnetic storage device; the interrogation bus is connected to the interrogation generator through the interrogation switch connected in its turn to the storage control circuit. The reset bus through the reset generator is connected to the output of the magnetic magnetic field recorder Gz. Short circuits of the device are the difficulty and slowness in the case of the necessity of combining the recording and scoring modes. The purpose of the invention is to increase the speed of action. The goal is achieved by introducing into the well-known buffer memory three groups of elements AND, elements of equivalence, elements INE, K-S triggers, drivers of write pulses and. counters, inverters, additional single-pulse generators, delay elements, AND elements, OR group, read bus, write pulse driver input connected to the write bus and S input of the first R-S trigger, single output of which is connected to the first input of the first element And, and the output pulse writer® output is connected through the first inverter to the first input of the second element, And the second input of the first element And is connected through the second inverter. With the output of the read pulse generator, which input is connected n to the readout bus to the 5 input of the second R-5 flip-flop, the single output of which is connected to the second input of the second element AND, the outputs of the AND element are connected respectively to the external single-pulse generator, the output of the first additional single-pulse generator is connected to the write input of the storage device, first the inputs of the elements of the first group and through the first delay element to the counting input of the write address counter and R to the input of the first R-S flip-flop, the output of the second additional generator of primary pulses To the 1st input of the third R- 5 flip-flop, the 6-input of which is connected to the R-inlet of the second R-STRIP, the counting input of the counting address counter and the output of the second delay element, the input of the second delay element connected to the output of the single-pulse generator and the first inputs of the elements AND the second group, the second inputs of this element are connected to the outputs of the read address estimator and the first inputs of equivalence elements, the second inputs of the telephone are connected to the corresponding outputs of the address counter of the address and the second inputs The elements of the first group, the outputs of elements of equivalence are connected to the inputs of the NAND cell, the output of which is connected to the first input of the third element I, the second input of which is connected to the inverse of the third R-S trigger, and the output to the input of the generator of single pulses, the outputs of the elements Both the first and second groups are connected respectively to the first and second inputs of the OR elements, the outputs of which are connected to the drive's address inputs, the outputs of the output register are connected to the first inputs of the AND elements of the third group, the outputs of which L are output devices, and the second inputs of AND gates of the third group are connected to the read bus. The drawing shows a functional diagram of the BZU. The device contains a drive 1, input 2 and output 3 registers, drivers 4 and 5 write pulses, and read, counters 6 write and read 7, first 8, second 9 and third 10 groups of logic elements AND group 11 elements OR, And logical elements 12 equivalence, AND IS input logic IS 13, single pulse generator 14, control RS trigger 15, RS write and read triggers 16, first 18, second 19 and third 20 AND gates, first 21 and second 22 , the first 23 and second 24 inverters, the first 25 and Torah 26 delay elements. The information inputs of the accumulator 1 are connected to the outputs of the input register 2, and the information outputs of the accumulator through the output register 3 are connected to the first inputs of electric power supply AND of the third group 10, the outputs of which are inputs of the device. The second inputs of the elements And 10 are connected to the readout bus of the device. The device write bus is connected to the input of the rammer 4 and the S-input of the trigger 16, and the output of the rammer 4 through the inverter 23 is connected to the first input of the second element AND 19. Single: the output of the trigger 16 is connected to the first input of the first element And 18. The readout bus is connected to the input driver 5 and S - input of the trigger 17. The output of the driver 5 through the inverter 24 is connected to the second input element And 18, and the single output of the trigger 17 is connected to the input of the second element And 19.

The output element And 18 connected to the generator 21 single pulses (GOI), the output of which is connected to the input element 25 of the delay, the first inputs of the elements And the first group 8 and the recording input of the drive 1.

The output of the delay element 25 is connected to the R input of the trigger 16 and the counting input of the counter 6 of the extinguish address, the outputs of which are connected to the second inputs of a group of 8 elements and the second inputs of the equivalence elements 12.

The output of the element And 19 is connected to the VS81 HS 22, the code of which is connected to the R-BXoqy trigger 15, whose 5-input is connected to the R-BXooy trigger 17, the counting input of the counter 7 addresses schita. and the output of the element 26 aaozhki. The input element 26 of the delay is connected to the output of GOI 14, vhotsu. readout of battery 1 and the first group of 9 elements I, the second inputs of which are connected to the outputs of the counter 7 and the first inputs of the elements 12 of equivalence. The outputs of the elements 12 are connected to the inputs of the circuit AND-NOT 13, the output of which is connected to the first input of the element I 2O, and the second input of this element is connected to the inverse of the trigger 15,

The output of the element And 20 is connected with the input of the YI 14. The outputs of a group of 8 elements And are connected to the first inputs of a group of 11 elements OR, and the second inputs of this group of elements are connected to the outputs of a group of 9 elements I.

The outputs of the group of 11 elements OR are connected to the address inputs of the drive t

The device works as follows.

In the INITIAL state, the counters are 6 write and read addresses 7 as well. the triggers 15-17 are set to zero, the input information is contained at the inputs of the input register ii and, accordingly, at the information inputs of accumulator 1.

Work BZU begins with the recording mode.

The write pulse arrives at the if input of the record trigger 16 and puts it into a single state, opening the element I 18 at the first input. In the absence of a read pulse, a logical unit is present at the output 24, so when the trigger 16 is turned on, the output voltage of the element 18 appears to have a positive voltage drop across which the GOI. 21 generates a write pulse. This impulse opens logical elements of the first group 8 and allows the code from the outputs of counter 6 to be written to the address inputs of accumulator 1. In addition, this impulse records the initial information to the accumulator at the address of counter 6 of the recording address (in this section; zero). At the end of the write cycle to the drive, the same write pulse delayed by the delay element 25, resets the write trigger to O and increases the contents of the 6 write address counter to.

In the result of exceeding the contents of counter 6 of the write address over the contents of counter I of the readout address, a negative differential appears at the output of multi-valued element 12 corresponding to the lower order of counters 6 and 7, causing a positive voltage drop to not occur at the output of the VI-input circuit AND -NE 13. As a result of coincidence of voltage drops A mismatch and a single cocTost of the inverse shoulder of the trigger 15 at the output of the element I 2O, a positive voltage drop occurs, according to which LI 14 produces a pulse with Stiffing This pulse opens the second group of 9 elements AND, having connected the outputs of the counter 7 of the read address through the circuits AND 9 and OR 11 to the address inputs of accumulator 1 ,. as a result of which the information from the accumulator to the output register is read, then this pulse, delayed by -e / delay 26, confirms zero state of read trigger 17, sets trigger 15 into one state, prohibiting the potential from passing The mismatch through the element Both 20 and increases the content of the read address counter 7, which leads to the coincidence of the codes in the 6 and 7 counters. Sladadno, the potential Disagreement at the output of NAND 13 disappears. This completes the write-read cycle of the first information word.

Similarly, with the arrival of any next write pulse, 3 letters are written to drive 1 of the second and subsequent information words, and a potential for a Disagreement is established at the output of the NAND 13 element. In this case, in any case, only one readout occurs, since after the first readout, the trigger 15 is set and the AND 2O element is locked. 79 When reading information from the output register, a read pulse is sent to the read bus, which permits the extraction of information from the output register through the I 10 output device. At the same time, this pulse is set to read trigger 17. If there is no write pulse on the write bus, then logical I is present at the output of the inverter 23, and when positive differences coincide at the inputs of the AND 19 element in the GSIZ 22, a pulse appears that sets the 1 inverse output of the trigger 15, allowing the potential There is a mismatch at the input of GOI 14 and the readout of the second information word. From the accumulator to the output register. The impulse from the GOI 14 also resets the trigger 17 readings, increases the content of counter 7 by one and locks the power amp I 2O by setting 1 trigger 15, the read process continues Yo until the codes in counters 6 and 7 coincide and reset potential mismatch. At this point, the works of the BZU end. The write-read process in BZU occurs asynchronously, i.e. The write and read pulses on the write and read buses appear at any time, as determined by the operation of external control devices. In the case of the write pulse arrival, during the read time, the write block is blocked for the duration of the read cycle on the second input of the element 18, while the duration of the read cycle is determined by the duration of the pulse of the driver 5, which through the inverter 24 enters the second input of the element 18. reading during the recording using the pulse shaper of the write cycle 4, the inverter 23 and the first input of the And 19 element. The above interlocks do not lead to the loss of information words, but only produce Constructing and reading moments of each other relative to each other without slowing down the speed of the device. Compared with the known, the proposed device has a large quick action due to the possibility of bathing the baths from the storage device during moments of pauses between the recordings to the storage device. Reading from the read pulse on the YuU has a minimum delay, since it is determined only by the delay of the operation of one element I. of the invention. The storage device containing the drive, the information inputs of which are connected to the corresponding outputs of the input register, and the outputs are connected to the inputs of the output register, the counters write and read addresses, a single pulse generator and a write bus, characterized in that, in order to increase the speed of the device, three groups of elements I, E cients equivalence, NAND, i -5; triggers, write pulse formers and readouts, inverters, additional 70: pulse generators for night-time pulses, elements of delay And elements, group of elements OR, read bus, the input of the fmirder of write pulses connected to the non-write and S-input of the first R - S trigger, the unit output of which is connected to the first input of the first element I, and the output of the write pulse former is connected through the first inverter to the first input of the second element I, the second input of the first element I is connected via the second inverter with the output form the pulse pad is read out, the breeze of which is connected to the read bus and the S-BXotiy of the second 5 is S. trigger, a single output of which is PUSHED: to the second input of the second element AND, the outputs of the elements AND are connected respectively to the inputs of the additional single-pulse generator, the output of the first additional single-pulse generator connects to the recording channel of the accumulator, the first inputs of the And elements of the first group and through the first delay element to the counting input of the write address counter and the input of the first RS trigger, the output of the second post-generator single pulse generator is connected to the R input of the third R-S trigger, $ input to Ogoy is connected to R-exotiy of the second R-S trigger, the counting input of the read address counter and the code of the second delay element, whose input is connected to the output of the single pulse generator, I connect the drive and the first inputs of the second group And elements, the second inputs of which are connected to the output of the counter the read addresses and the first inputs of elements of equivalence, the second inputs of which are connected to the corresponding outputs of the write address counter and the second inputs of elements AND of the first rpyn-s py, and the outputs of the output terminals are equal Parameters to the inputs of the NAND element, which is connected to the first input of the third element I, the second input of which is connected to the inverse output of the third to -R-6 flip-flop, and the output to the input of the generator of single pulses connected to the first and second groups to the first and second inputs of the OR elements, the outputs of which are co-is dinene with the drive's input inputs, the outputs of the output register are connected to

the first inputs of the elements AND the third group, the outputs of which are $ 1VL5pots by the outputs of the device, the second inputs of the AND elements of the third group are connected to the readout bus.

Sources of information taken into account in the examination

1. Author's certificate of SSHZR

N 487417, cl. Gr 11 C And / On, 1975.

2. Authors certificate of the USSR M 493805, cl. Q II C 7/00, 1975,

3. Authors certificate of the USSR N 273284, cl. About II C 11/06, 1970 (prototype).

Claims (1)

Claim A buffer memory containing a drive, informational inputs of which are connected to the corresponding outputs of the input register, and the outputs are connected to the inputs of the output register, the write and read address counters, a single pulse generator and a write bus, characterized in he entered three groups of elements AND, elements of equivalence, the element AND-NOT, I? -5 _: triggers, write pulse drivers and readouts, inverters, additional single-pulse generators, delay elements, AND elements, group of OR elements, read bus, with the input of the write pulse shaper connected to the write bus and the first I input ? - £ trigger, a single output of which is connected to the first inlet of the first element And, and the output of the write pulse shaper is connected through the first inverter to the first input of the second element And, the second input of the first And element is connected through the second inverter to the output of the read pulse shaper, whose input is connected to bus read and 5-input second b? - 5 flip-flops, a single output of which is connected: to the second input of the second element And, the outputs of elements And are connected respectively to the inputs of additional generators of single pulses, the output of the first additional generator of single pulses is connected to the recording input of the accumulator, the first inputs of elements And of the first group and through the first element delays - to the counting input of the write address counter and to the input of the first K-5 trigger, the output of the second additional single pulse generator is connected to the input of the third ί? - 5 trigger, the 5th input to Secondly, it is connected to the K-input of the second K-5 trigger, the counting input of the read address counter and the input of the second delay element, whose input is connected to the output of the single pulse generator, the drive's read input and the first inputs of the AND elements of the second group, the second inputs of which are connected to the output 9 942132 aam read address counter and first inputs of equivalence elements, the second inputs of which are connected to the corresponding outputs of the write address counter and second inputs of AND elements of the first group, and outputs of equivalence elements connected to the inputs of the AND-NOT element whose output is connected to the first input of the third element I, the second input of which is connected to the inverse output of the third "o-B-5 flip-flop, and the output - with the input of a generator of single pulses, the outputs of the elements of the first and second groups are connected respectively to the first and second the inputs of OR elements, outputs of which are soy-dineny and storage, with address inputs, the output register outputs are connected to ten the first inputs of the elements of the third group, the outputs of which are the outputs of the device, the second inputs of the elements of the third group are connected to the read bus.