SU674014A2 - Digital null indicator - Google Patents

Description

I

The invention relates to a pulse technique.

The main author's certificate No. 335685 describes a digital zero body containing a converter code time interval formed by the reference frequency generator, m hIt 1s zim Schegchikok, code transfer circuit, gate, trigger and three delay lines, period meter formed by pulse counter, register a memory, a first code circuit, a prohibition circuit, and two delay lines, a pulse shaper, and a coincidence circuit. The inputs of the latter are connected to the first output and through the pulse shaper to the second input of the converter the code-time interval, the third and fourth outputs of which are connected to the first and second inputs of the period meter, the output connected to the first input of the converter, and the terminals of the device are connected respectively to the third input measure tel pfiod n to the second input of the converter.

The disadvantages of an aan device are the lack of information about the magnitude and sign of the frequency and period deviation and the lack of memory rating.

The aim of the invention is to obtain information on the magnitude of the sign of the frequency and period deviations and increase the noise immunity of the null organ.

A delivered ael is achieved by introducing a logic signal processing block into a digital null organ, the output of which is connected to the converter input, the time interval, the second to the input of the unit and the period interval, and the inputs are connected to the input signal buses, two additional triggers, two a valve, two logical elements OR, two lines at the top and a result counter, the inputs of which are connected to the output of one remote valve directly and the other through the first of the additional delay lines. And the first

the input of each of the valves is connected to the output of one of the triggers, the second inputs of the additional valves are connected to the outputs of the code-time interval converter, one input of the first 10 additional trigger is connected to the additional output of the code-time converter, and the other input - with the output of the first additional logic element OR, one input of which is connected to the output of the second additional valve, and the other input to the output of the second auxiliary logic element OR and the first input of the second complement a second trigger, the second input of which through a second additional delay line is connected to the output of the code-time interval converter, while one input of the second additional logic element OR is connected to the output of the logic element I.

The logic signal processing unit contains successively connected coincident pulse exclusion unit, a b1 reading and a trigger; the first output of which is connected to the inputs of the first and second, and the second output. " The inputs of the third of the second and fourth valves, while the second inputs of the first and third valves are connected to one input, and the second inputs of the second and fourth. - to another input of the logic processing unit, the outputs of the first and fourth valves are connected to the inputs of one, and the outputs of the second and the third to the inputs of another logical element OR.

The structural electrical circuit of the described null organ is shown in the drawing.

The zero-body contains a code-time interval 1 converter, consisting of a generator of 2 pulses, a counter 3, a code input valve 4, a trigger 5, a valve 6, an OR 7 logic element and delay lines 8.9.1 O, a period measurement unit 11, consisting of a counter 12, a storage register 13, a code input 14., a prohibition logic element 15 and delay lines 16, 17, a logic processing unit. 18 of the signal, consisting of the block of the exclusion of 19 coincident chi pulses, the subtractor 20, the trigger 21, the gates 22-25, the logical elements OR 26.27, the form 28 pulses, logical. element And 29, add a trigger 30, 31, valves 32, 33, logic elements OR 34, ZE, pin delay 36, 37 and counter 38. The compared signals are fed to tires 30, 4О. The output {signals are removed from the outputs.

The device works as follows.

Input compare signals in the form of a sequence of pulses, the following frequencies | and f j are fed to the input buses 39 and 4O, the logic processing unit 18, regardless of the input frequency ratio, always forms a larger ft and a smaller f of the input frequencies and allows the zero-organ to function normally regardless of the ratio of input frequencies, their phases and their speeds. The main assembly of the unit 18 is the reader 20, which can be performed, for example, according to the well-known scheme of a trigger and two gates (not shown) at its outputs. The flow of pulses at one of the outputs of the subtractor indicates that the frequency exceeds the frequency nocrynaic at its corresponding input. Difference-frequency pulses, depending on the sign, are formed at the outputs 43 and 44.

For normal operation, the subtractor 20, with the arrival of coincident pulses, is an exception block 19, which pushes the simultaneously pulsed pulses in time. If a . then the signals from the trigger 21 open the valves 22 and 23, if f 1, then the signals from the trigger 21 open the valves 24 and 25, while: the pulses f and fi are input to either the code-time converter 1, or the period measurement unit eleven.

Thus, regardless of which of the input frequencies is higher, there is always a higher frequency at the input of the period measurement unit, and the code-time interval at the input of the converter is smaller.

Claims (2)

The pulses with a higher frequency fg are fed to the input of the period measurement unit 11, in which each period is quantized by the larger of the input frequencies by the reference frequency pulses ig of generator 2, Each pulse Ig through the prohibition logic element 15 in the absence of a inhibitory signal from the output of the delay line 9 zeroes the memory register 13, then, for holding in delay line 16, rewind. The new code value from counter 12 is opened into the storage register 13 through the opening gate 14 and, after a delay in the delay line 17, zeroes & the counter 12, after which it is filled with reference frequency pulses from the generator No. 2 output. Since the time interval t between successive The zeroing of the meter 12 is equal to the current period of the high frequency T m {5 code obtained by the time the counter is zeroed. proportional to the period of greater frequency. The code of the terminating period of the higher frequency is stored in the storage register 13 until the end of the next period. Each pulse i of a lower frequency is fed from the output of logic processing unit 18 to the input of the converter time-interval 1, This impulse passed through the logical element OR 7, the trigger 5 is set to the position at which the valve 6 closes. After a delay in the delay line 8, the pulse i zeroes the counter 3. Then, after passing the delay line 9, the pulse opens the valve 4, through which the reverse code N more is recorded from the memory register 13 into the counter 3, passes the delay line 10, the pulse converts the trigger 5 to the delay, open in The firing valve 6, through which from the output of the generator 2 to the counting input of the counter 3, the reference frequency to begins to flow. Since counter 3 records the number M, the description of it from counter 3 occurs at a time interval .. equal to the period of the higher frequency if the impulse to write the number from counter 3 through a logical element OR 7 sets trigger 5 to the position that closes the valve 6. Thus Converter 1 performs the functions of a code converter received in a period measurement unit 11 in a time interval equal to the period of the larger input frequency. The device starts to work on a start signal supplied to the input of the logic element OR 35. Output GOVERNMENTAL signals in OR gates 34 and 35 are the triggers 30 and 31 are set to the initial position, at which the valves 32 and 33 closed. The first impulse of lower frequency from the no. Ixoaa logic processing unit 18 starts the converter 1 and delayed in delay lines 8, O and 10 arrives at the inputs of the logic element I 29, valve 33 and through the delay line 37 at the input of trigger 31. Since gate 33 is closed , then the first pulse does not pass through it, but after a delay in the delay line 37, flip-flop 31 moves to the position of the outgoing gate 33, through which the second and all subsequent pulses pass. Since in the code-time-Interval 1 transducer a time interval T мень of a smaller period is formed, and it is launched into operation with large frequency pulses with a period T5., Then the output signal of the transducer is formed earlier when the second pulse travels from the counter 3 output to the trigger 30 opening the valve 32 with its signal. The second pulse is released through the open valve 33 and through the OR 34 gate to the second input of the trigger 30. At the same time, the valve 32 is closed. Thus, the time between the arrival of a pulse from the output of the converter is a code-time interval and the second pulse of frequency i. which opens the valve 32, is equal to the difference of the periods of the compared signals | DT | T5-T iTj-Trl. Since the second; impulse; i also starts the converter at time interval 1, then after time Tj ,, a new impulse is formed on its output, opening valve 32 and repeating the measurement cycle. Thus, for a time not exceeding the larger of the periods of the compared signals, a time interval equal to the difference of the periods of the input signals is formed at the output of the trigger 30. During the time dT, the reference frequency 38 receives the reference frequency pulses and, by the end of the measured interval, a code is formed at its outputs proportional to the difference between the periods. -wired signals. After completion of the measurement, this code from counter 38 is rewritten into the register of memory (not shown in the diagram) and the counter 38 is wrapped with a signal from the output of the delay line 36, preparing for a new measurement cycle. When the IT is approached, the magnitude of dT decreases and at T ... T.j the signals at 1 go of counter 3 and delay line 10 appear simultaneously. In this case, the logic element AND 29 is triggered and at its output a signal (d1 O) of the equality of the power signals is generated. To take into account the dynamics of signal changes, the pulse from the output of the code-time converter, interval 1, is extended in the pulse shaper 28. The signal u.i OS of the output of the logical element AND 29 nocrynaeiT to the input logical G6 of the element Id LI 35, set the device blocks to the initial position. In the described zero-organ, in addition to the coincidence signals of the compared signals by the value of L1, the signals of the difference of the matched signals by the frequency i d1, the signs of dissolution of the sigfn AfI are formed. The difference of the periods I DT I and the code of the difference of the periods. Claims 1. Digital null-organ auth. swith No 33568S, characterized in that, in order to obtain information 6, the magnitude and sign of deviation on the frequency and frequency and increase the noise immunity, a logical signal processing unit is entered, the first output of which is connected to the input of the transmitter, the time interval, the second - to the input of the block and; a period period and inputs are connected to input signals, up to two triggers, two valves, two OR logic elements, two delay lines, a result counter, the inputs of which are connected to the output, one additional valve mediocrely and the other through the first of the additional supply lines, the first input of each of the gates is connected to the output of one of the flip-flops, and the second inputs of the additional gates are connected to the transmitter outputs of a code-time interval, one input of the first additional flip-flop is connected to the additional output of the converter -time interval, and the other input - with the output of the first additional logic element OR, one input of which is connected to the output of the second additional valve, and the other input - from the output The second additional logic element OR or the first input of the second-year trigger, the second input of which is connected to the converter output through the second additional line; the time interval, while one input of the second additional logical element OR is connected to the output of the logic element. AND. 2. A digital zero-organ pp. 1, characterized in that the signal processing unit contains in series a block of exclusion of coincident pulses, a shpattel and a trigger, the first output of which is connected to the inputs of the first and second, and the second output to inputs of the third and fourth valves, while the second inputs of the first and third valves are connected to one input, and the second inputs of the second and fourth - to another input of the logic processing unit, the outputs of the first and fourth valves are connected to the inputs of one, and the outputs are second and third. - to the inputs of another logical element OR, . ... “- | 5) b