SU936433A1 - Difference-type pulse counter - Google Patents

Description

t

The invention relates to a pulsed technique that can be used for repainting and technical means in this field, for example, in measuring devices for amplitude parameters.

signal.

The difference pulse counter is known, which allows to obtain the difference in the forward code when two packets are subtracted.

with an arbitrary number of pulses, 10

containing counting decades, blocks of zero-decade detection, triggers and driver, which includes a generator, the frequency of which generation exceeds the frequency of counting im-, n, pulses of Cl.

A disadvantage of the known device is its relatively low speed.

A known difference pulse counter, comprising an input bus, a reversible counter, an impuls distribution unit, a control unit, a trigger, the counting input of which is connected to the first output of the control unit, whose input is connected to the input bus and to the first, second inputs of the distribution unit pulses, the third and fourth inputs that are connected to the direct and inverse outputs of the trigger, respectively, the first and second outputs of the pulse distribution unit are connected respectively to the clock inputs of the addition and subtraction reversely go counter 2}.

Claims (2)

However, the performance of such a counter is not high enough. The maximum settling time of the entire counting occurs at the moment of transition from the state to the state O and is determined by the total time of setting the reversible pulse counter, the decoder, the control unit to the third sign, which limits the frequency of the counting pulses, since the time the counter transitions from condition O state is not known in advance. Decreasing the frequency of the counting pulses, the existence of a measurement lengthens the time, especially with a wider averaging that can be made from the results of 1OO, 1OOO and more measurements. The purpose of the invention is to increase the speed by the difference in the pulse counter. The goal is achieved by the fact that a difference pulse counter containing an input bus, a reversible counter, a pulse distribution unit, a control unit, a trigger, a counting input which is connected to the first output of the control unit whose input is connected to the input bus and to the first and second inputs Impulse distribution unit, the third and fourth inputs of which are connected with the direct and inverse outputs of the trigger, the first and second outputs of the pulse distribution unit are connected respectively to the clock inputs the addition and subtraction of a reversible counter; three IS-NOT elements, an additional trigger and an OR-NOT element, the first, second inputs and output of which are connected respectively to the transfer outputs, the reversing counter loan and the first input of the first input and the output of which is connected respectively to the control output of the control unit and to the installation input zero of an additional trigger, the installation input in which it is connected to the reset input of the reversible counter and to the third output of the management control unit, the fourth output one of which is connected to the first inputs of the second and third elements of the IS-NOT, the second inputs of which are connected respectively to the direct and inverse outputs of the additional trigger, the outputs of the second and third elements of the IS-NOT are connected respectively to the inputs of the unit and zero of the trigger. The pulse distribution unit contains two IS-NE elements, the first inputs are connected respectively to the first and second inputs of the pulse distribution unit, the third and fourth inputs of which are connected respectively to the second inputs of the first and second IS inputs, the output of which are connected respectively to the first and the second outputs of the pulse distribution unit. FIG. 1 shows the scheme of the proposed device; in fig. 2 - time diagrams of signals at characteristic points of the circuit. The device contains a reversible counter 1, trigger 2, pulse distribution unit 3, consisting of AND-NOT elements 4 and 5, additional trigger 6, OR element 7, AND-NOT elements 8-1О, control block 11, input bus 12, the input 13 of the control unit 11 and the outputs 14-17 of the control unit 11. FIG. 2 denotes: a timing diagram of 18 signals on the input bus 12; timing diagrams 19-22 signals respectively at the outputs 14 17 of the control unit 11. FIG. 1 input bus 12 is connected to input 13 of control unit 11 and to the first inputs of elements 4 and 5 of AND-NOT, the second inputs of which are connected respectively to the forward and inverse outputs of the trapter 2, the installation inputs to zero, and the counting input of which are connected respectively with the outputs of elements 9 and 1O AND-NOT and with the output 14 of the control unit 11, the output 16 of which is connected to the installation input to the unit of additional trigger 6 and to the reset input of the reversible counter 1, the clock inputs of addition, subtraction, the outputs of the loan and transfer are connected according to Actually with the outputs of elements 4 and 5 of the NAND, with and the second inputs of the element 7 Ida-NOT, the output of which is connected to the first input of the element 8 AND-NOT, the second input and output of which are connected respectively to the output 15 of the control unit 11 and the installation input to zero of the additional trigger 6, the direct and inverse outputs of which are connected respectively to the first inputs of elements 9 and 10 of NAND, the second inputs of which are connected to the output 17 of the control unit 11. The device works as follows. The control unit 11 forms, at its outputs, as the pulse packets arrive at the input (Fig. 2, chart 18), enveloping them (Fig. 2, chart 19) and by dividing the pulse frequency of the bob into two, generates pulses corresponding to the even packets n ( Fig. 2, diagram 20), on the falling front of which forms a short pulse (Fig. 2, chart 21) to implant the zero setting (Fig. 2, chart 22), which is delayed relative to the short pulse by the value of its duration. Consider the possible options for the device. Blank trigger 2 is in the zero BOM state at the moment of arrival of the zero setting pulse. The inverse output of flip-flop 2 is present 1, and the first packet of input pulses (Fig. 2, diagram 18) through the element 5 AND-NOT goes to the clock input of the reversing counter 1. Receipt of each counting pulse reduces the counter content by one (for the case of a ten-fold reversible counter O-v 9-v8-.,.). As a result, the reversible counter 1 is in the state corresponding to the additional code of the number m. According to the OKOI of the burst of pulses, the decrease in the pulse coming from the output 14 of the control unit 11 (Fig. 2, diagram 18) changes the state of the trigger 2 to the contraindicate, i.e. translates it into a single state. At the direct output of triter 2, the second bundle of n input pulses (Fig. 2, diagram 18) appears through the element 4 and IS NOT to the clock input of the addition of a persistent counter 1. The arrival of each counting pulse increases the counter content by one . Let n m m. Then the increase in the contents of the counter psmshoditsya way: ... -2- .... At the same time, the difference n-t was obtained in the forward code. At the moment of transition 9, a transfer pulse is generated at the transfer output: reversible counter 1, which through element 7 OR-NOT arrives at the first input of element 8 AND-H at the second input of which there is a signal from output 15 of control unit 11 of control unit (Fig. 2, diagram 20), since during a packet of n pulses, the signal at the output 15 of the control unit 11 has a level 1 pulse from the output of element 7 OR-NOT through element 8 AND IS NOT to the input of the zero setting of the trigger 6, set the latter to zero state the At the inverse output of the trigger 6 appears 1. After the end of the second pack, the fall of the pulse coming from the output 14 of the control block 11 (Fig. 2, diagram 19) changes the state of the trigger 2 to the opposite, i.e. translates it into zero with. Following this, the signal C of the output 17 of the control unit 11 (Fig. 2, diagram 21) through the element. 10I-NOT arrives at the setup input to zero of trigger 2, setting it to the zero state. Since at this moment trigger 2 is already in the zero state, switching it does not occur. Next comes a signal (Fig. 2, Chart 22) which sets the reversible counter 1 to the zero state and the trigger 6 to the one state, after which the described operation cycle of the device is repeated. Now let m p. In this case, the contents of the counter, increasing, do not reach the zero state, and the difference is present in the reversible counter 1. in the additional code. In addition, the reversible counter 1 does not generate a transfer pulse, with the result that trigger 6 remains in the normal state and there is a level at its forward output. The signal from the output 17 of control unit 11 (FIG. 2, diagram 21) through element 9 I- It does not arrive at the input of trigger 2, it is set to one. Thus, the second cycle of operation of the device begins with the addition. At the same time, the contents of the counter are increased as follows .... After the end of the first batch of pulses, trigger 2 changes its state to the opposite and the second batch of pulses reduces the contents of the counter: m m - ...- m-n. As a result, the difference m-n is present in the reversible counter 1 in the forward code, since m -7 p. Further, the cycle of operation of the device is repeated. Let the trigger 2 be in the single state at the moment of arrival of the output 16 of the control unit 11 (Fig. 2, diagram 22). In this case, the cycle of operation of the device begins with the addition. This case is described for m 7 p. Now let m p. The cycle of the device starts with the addition: 1- 2- ... -vm. After the end of the first burst of pulses, the trigger 2 switches and subtracts; t-m - 1 -... .... Since m p, the difference is represented in the reverse counter 1 in the additional code. At the time of transition About 9 at the exit of the loan revsivny. counter 1, an impulse is formed which "gray" sets trigger 6 to the zero state. Signal from the output. 17 of the control unit 11 ((} ig. 2, diagram 21), through AND-NOT element 10, enters the input of setting zero of trigger 2, sets it to the zero state, and the next operation cycle of the device starts with subtraction: O-. At the same time, the loan impulse formed at the moment of transition 9 does not pass through the element 8 AND IS, since output 15 of control unit 11 (Fig. 2, diagram 20) is present at this moment O. After the end of the first batch of pulses, trigger 2 switches the contents of the counter 1 starts u & li +: + 1- ... lv ... -rn. The difference n -m is present in the count ke 1 in the forward code, since P m. At the moment of transition 9-O, a transfer pulse is formed, which sets the trigger 6 to the “normal” state. The pulse from the output 17 of the control unit 11 (ig. 2, diagram 21) through element 10 I-NOT sets trigger 2 to the zero state, however, switching of trigger 2 does not occur, since the latter, after the windows, the second burst of pulses does not go to the zero state. The following described cycle of operation of the device is repeated. Regardless of the initial match and the number of pulses in the packs, the device allows to obtain the difference in the direct code, starting from the second measurement cycle. The maximum frequency of the counting pulses is determined by the speed of the logic elements used in the device. Loss of one measurement cycle occurs only when the sign of the difference m - n changes, which is possible, for example, when another signal is applied to the input measuring meter, or when other measured points of the signal are selected. At the same time, the measurement time is due to the loss of one measurement cycle in the presence of digital averaging over the results of 10O; 1OOO; By 1 mesh increases by just 0.01; O, O01; 1 / K respectively. This makes it possible to achieve a higher speed than the known. Claim 1. The differential pulse counter containing an input bus, a reversible counter, a pulse distribution unit, a control unit, a trigger, the counting input of which is connected to the first output of the control unit, the input of which is connected to the input busbar and the first and second inputs of the imputut distribution unit, the third and fourth inputs of which are connected respectively with an input signal and inverse outputs of a trigger, the first and second outputs of a pulse distribution unit are connected respectively with clock inputs of addition and subtraction A versatile counter, characterized in that, in order to improve speed, three AND-NOT elements, an additional trigger and an OR-NOT element are introduced into it, the first, second inputs and output of which are connected respectively to the transfer outputs, the reversible counter loan and the first input of the first NAND element, the second input and output of which are connected respectively to the second output of the control unit and to the installation input zero of an additional trigger, the installation input to which is connected to the reset input of the reversible counter and the third the output of the control unit, the fourth output of which is connected to the first inputs of BTOjtoro and the third IS-NOT elements, the second inputs of which are connected respectively to the forward and inverse outputs of the additional trigger, the outputs of the second and third IS-NOT elements are connected respectively to the unit inputs and zero trigger 2. The counter according to claim 1, that is, that the distribution unit of the multiplexes contains two AND-NOT elements, the first inputs of which are connected respectively to the first and second inputs of the pulse distribution unit, the third, fourth inputs which are connected respectively with the second inputs of the first second elements AND-NOT, the outputs of which are connected respectively with the first and second outputs of the pulse distribution unit. Sources of information taken into account in the examination 1. Authors sdidedelstao USSR Jvfe 572934, cl. “03 K 23/02, 1977. 2. Authors certificate of the USSR 666646, cl. H 03 K 23 / O2, 1979 (prototype). Sh P P 18