SU922875A1 - Shift register monitoring device - Google Patents

Description

The invention relates to digital computing and can be used in hardware control devices of logical computer nodes, as well as in digital signal processing - in radar, communications, telemetry and in other areas of digital technology.

A device for controlling shift registers is known, which contains two delay elements, a parity unit, a control unit, a comparison unit, a convolution node, and a trigger [1).

The disadvantages of this device include a significant amount of equipment and low speed, determined by the used delay line.

The closest to the proposed technical entity is a device for controlling the shift register, containing the input and output estimated triggers, parity trigger, a convolution node modulo two, whose inputs are connected to the outputs monitored2

The second register is modulo two, the four inputs of which are connected respectively to the outputs of the flip-flops and the module of the convolution modulo two.

In each cycle of operation of this device, the parity of the register contents calculated in the convolution node is compared in the modulo two adder with the predicted parity formed in the same adder from the word parities counted in the triggers, inserted and pulled out of the register, and the parity of the original word recorded in the trigger parity.

The device allows to detect errors of the shift operation and the operation of the parallel writing of information into the register [2].

A disadvantage of the known control device is the presence of a convolution node modulo two per η inputs, the volume of which is proportional to the digit capacity of the controlled shift register p.

When hardware implementation volume

3 .922875 4

The equipment of the control device turns out to be very significant and comparable with the volume of the controlled register. This leads to a decrease in the reliability of the control circuit, because the probability of shift errors in the register can be of the same order as the probability of the layers in the bulky control circuit.

The purpose of the invention is to simplify the device.

This goal is achieved by the fact that in the device for controlling the shift register containing the first, second and third triggers, the first inputs of which are connected to the first control bus, modulo two, the output of which is the output of the device, the second inputs of the first and second triggers connected to the appropriate. device inputs, the second input of the third trigger is connected to the device information bus, and the second control bus, a fourth trigger is entered, the first input of which is connected to the output of the first trigger, the second input of the fourth trigger is connected to the first control bus, the first input of the modulo two is connected to the output of the fourth trigger, the third input of which is connected to the second control bus, the third input of the third trigger is connected to the first control bus, the second input of the modulo two adder is connected to the second control bus i, the outputs of the second and third triggers "connected to the third and fourth inputs of the modulo two adder.

The drawing shows a functional diagram of the device.

The device contains triggers 1-4, the adder 5 modulo two, controlled. shift shift register 6, shift register 6 inlet 7, control buses 8 and 9, information bus 10, shift control bus 11 and shift code tires 12 (input buses).

Bus 8 receives a write control signal, bus 9 ~ a reference signal, bus 10 a parity bit signal.

The device works as follows.

Trigger 1 calculates modulo two quantities of units to be moved to the controlled shift register 6, trigger 2 counts the units to be moved out of the register, and trigger 3 stores the parity bit of the original word used in register 6 on the input buses 12. Modulator 5 modulo two before the comparison signal on bus 9 once per η clock cycles (where n is the width of shift register 6), modulo two parities of the original word (the contents of trigger 3), the output word (contents of the trigger 2) and parity

The input word delayed by η clock cycles in trigger 4. If the shift in register 6 is executed correctly, the signal from the output of adder 5 is zero, in the pouring case, adder 5 generates a signal of a shift error.

• In the first cycle of operation of the device, the recording control signal on bus 8 records the parallel code VI into the register and resets the trigger _} 1-4. The trailing edge of the pulse on ι bus 8 (at the end of the first clock cycle) is written in the trigger 3 bits of the parity of the word VI.

In each following tact of work on

5 (n + 1) and inclusive of the signal information on the bus is a shift register 6 and retracts count parities XI and VI extendable n-bit words in the triggerah'1 2 and ₅ respectively governmental.

In addition, in the cycle (n + 1) on bus 9 a comparison signal is sent, which takes up the first half of the cycle and the next with the period p. By this signal, adder 5 modulo two with input control compares the counted (the contents of trigger 2) and the stored (contents trigger 3) the parity of the number VI, thereby performing control information adopted in the register 6 shift. If the information is received incorrectly, an error signal is generated. In the same tact of working with the falling edge of the comparison signal on bus 9, trigger 4 is set to the position corresponding to parity calculated by jigger 1, which is pushed into register 6 of word XI. and stores it η ticks until the next comparison signal arrives on bus 9 (2 +1)

⁰ tact.

In the same cycle, the adder 5 adds modulo two parity of the word XI, pushed back into the register 6 η cycles back (the contents of the trigger 4), the total

' ⁵ (modulo two) the parity of the advanced words XI and VI (the contents of trigger 2) and the stored parity of the word VI (the contents of trigger 2) and the stored parity

5 922875 6

words vi (trigger content 3). If all η of the previous shifts in register 6 are correct, then the signal from the output of the adder is zero.

In each subsequent segment of η 5 clock cycles, the operation of the device is repeated until the next control signal arrives on the bus 8 by parallel recording in. register, when all triggers of register 6 are reset and the operation begins · ^{, 0}

at first.

Despite the fact that the parity check is performed once per η clock cycles, all one-time errors are detected with a probability of up to one, ^15, since this leads to a change in the parity of the word being pushed.

The use of the invention will significantly reduce the amount of controlled equipment, which does not depend on the digit capacity of the controlled register. When this is achieved, the unification of the control device, and as a result, it is convenient to use, the invariance of its structure to the ^25- digit register.

ί

When using the element base of the TTL SIS and the digit capacity of the register η =

-64 volume of control equipment does not exceed 20% of the register volume. This increases the reliability of the proposed control device in comparison with the known volume of which equipment under the same conditions sostav- ₃₅ wish to set up approximately 70% of the volume register.

Claims (1)

Claims device for register control shift, containing the first, second and third triggers, the first 'inputs of which are connected to the first control bus, modulo two adder, whose output is the output of the device, the second inputs of the first and second triggers are connected to the corresponding inputs of the device, the second input of the third trigger is connected to the information bus device, and the second control bus, characterized in that, in order to simplify the device, it introduced the fourth trigger, the first input of which is connected to the output of the first trigger, the second input of the fourth trigger pa connected to the first control bus, the first input of the modulo two adder is connected to the output of the fourth trigger, the third input of which is connected to the second control bus, the third input of the third trigger is connected to the first control bus, the second input of the modulo adder | Two are connected to the second control bus; the outputs of the second and third flip-flops are connected to the third and fourth inputs of a modulo-2 adder.