SU1432786A1 - Linear code decoder - Google Patents

Abstract

This invention relates to electronics and can be used in digital broadcasting. The purpose of the invention is to improve noise immunity by detecting errors of multiplicity t + 1 and higher. The linear code decoder contains a buffer register 1, an adder 2 modulo 2, a calculator of 3 syndromes, an arithmetic unit 4, a polynomial memory unit 5, a control unit 6, a masking unit 7, an error counter 8, a polynomial degree calculation unit 9, a comparison circuit 10. 3 hp f-ly, 4 ill. with "

Description

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 The invention relates to radio electronics and can be used in digital broadcasting. The aim of the invention is to improve noise immunity by detecting errors of multiplicity t + 1 and higher.

Fig, 1 shows the structural scheme of the proposed decoder; FIGS. 2-4 are schemes for implementations of a masking unit, a calculating unit for the degree of a polynomial AND the control unit: laziness, respectively;: The linear code decoder (FIG. 1) contains a buffer register 1, an adder 2 modulo 2, an arithmetic calculator 3 block 4, block 5 of the memory of a polynomial, block 6 of the control block 7 of masking, counter 8 out of turn, block 9 of calculating the degree of the polynomial and block 10 of the comparison.

Block 7 masking (figure 2) contains buffer registers And and 12, the trigger 13 and the elements 2I-OR 14 and 15.

The polynomial degree calculation block 9 (FIG. 3) contains the AND elements: 16.1-16, HI 17.1-17. (N-1), the Igor-18 cipher, and the triggers 19.1-I9.N. The control unit 6 (FIG. 4) contains an i counter 20 and a memory unit 21. The linear code decoder works as follows.

I The received n-bit combination I enters the drive and at the same time into the syndromes calculator, where the syndromes of the received combination are calculated. As soon as the accepted combination of: qi is fully recorded: in buffer register 1, in the calculator of 3 syndromes the calculation of syndromes ends. And the calculated syndromes are copied according to the signal from the control block 6 to ARI (1 metric block 4, where It is a polynomial of 6oKG (Z) whose degree is t or depending on the multiplicity of errors.The coefficients of the polynomial G (%) belong to the field GF (2) 5 where p. There can be 2 different polynomials G (Z). On the other hand, there may be different syndromes in total and therefore 2 different x adjacent classes, Pr this mt p - K,

Each adjacent class can be matched in one-to-one correspondence by a polynomial. Polynomials 0 (Z) corresponding to the errors corrected by the given code are called admissible.

the rest are unacceptable. All polynomials of the first degree correspond to a one-time error and, therefore, are admissible. But not all polynomials (3i (Z) of degree 2 and vppe are admissible polynomials, since Cj, i, where i i t, a C is equal to the number of i-fold errors.

If there are erroneous signals in the received combination, the degree of the S (%) is equal to i. The polynomial G (, in this case, has i different roots belonging to the OPC field). If the received combination contains it erroneous symbols, then the degree of the polynomial (5 (z) is less than or equal to t. The number of roots of the polynomial is always equal to the degree of the polynomial. But in this case not all the roots of the polynomial (5 (h belong to the field (TG (2) , some or all roots of a polynomial belong to some extension of the field GF ().

From the arithmetic unit 4, the error polynomial 3 (z) is rewritten into the memory unit 5, where the field elements are alternately inserted into it, and the decoded combination is read from the buffer register 1. Each readable 1 1 1u from the accumulator symbol corresponds to the GF field element being inserted into an error polynomial. (2) If, when substituting the next element, the error polynomial is turned to zero, then the character currently output from buffer register 1 is inverse, C block 5, a unit is fed to the input of adder 2 modulo two, which modulo two is added to cyNJMaTOpe 2 with the character coming from the buffer register I. Thus, the data code of the code combination is inverted, i.e. error correction occurs. The number of units tje. The number of correctable errors in the code combination, arriving from block 5 during the decoding time of one code combination, is counted in the counter 8 errors.

Suppose that block 5 contains an invalid polynomial. In this case, it may turn out that none of the elements of the GF (2) field are the root of the given polynomial, or the roots belonging to the GF (2) field, {less than the degree of the error polynomial, B In this case, it turns out that from the output of block 5 to the input of the counter of 8 errors and the adder 2 modulo two there are fewer units than the degree of the polynomial Ha6 (Z) i The degree of the polynomial C5 (z) is calculated in block 9 of the calculation of the degree of the polynomial The arithmetic unit 4 is recorded as an error polynomial.

At the end of the decoding cycle, the code combination in the comparison block 10 compares the readings of the 8 error counter and the polynomial degree calculation unit 9.

If the readings are the same, then the masking unit 7 from the comparison unit 10 receives the signal O. By this decoding signal, the code combination from the masking unit 7 now arrives at the output of the device. In addition, this combination is stored in a masking unit 7.

If the readings of the error counter 8 are less than the readings of block 9 calculate the degrees of the polynomial, then from block 10 of the comparison, the input of masking unit 7 receives signal 1. This code in masking unit 7 decodes the currently decoded code combination, since it has a faulty error pattern. . The output of the device arrives

Previously correctly decoded.

The code combination that was previously stored in masking unit 7.

Block 7 masking works as follows,

From the output of adder 2 modulo two to the input of the first buffer register 11, a decoded combination arrives, and the previous decoded combination is output from it, which is fed to the first information inputs of elements 2I-OR 14 and 15. As soon as the last symbol of the cobbine is written to the first buffer register P, from block 10 of the comparison, the trigger 13 receives a signal o, if the code combination is not

20 to the second buffer 1, register 12. Thus, the device’s output does not receive the decoded code combination at the moment (it contains an unrecoverable error combination), but

25 Previously decoded without errors or with a correctable error code combination.

The polynomial degree calculating unit 9 operates as follows.

From the arithmetic unit 4 to the input of block 9, the calculated coefficients of the error error are successively obtained. If the degree of a polynomial is 30

35

40

45

at t, t, e, the coefficient G of the polynomial O1chibok is not equal to zero, then trigger 19, NT is triggered. The logical 1 signal from its direct output goes to the decoder Ig, the signal from the inverse output of this trigger enters the I 17 elements, prohibiting the triggering of the I9, l-19 .. (Nl) Ti triggers,.,., Tt,, C a The output of these triggers to the decoder 18 receives a logical O signal. At the outputs of the decoder there is a signal corresponding to the binary number t.

If the coefficient is C. Oh, the signal from the inverse trigger output

errors, correctable errors occurred, allows trigly signal 1 to be triggered if an unrecoverable error combination is detected in this code pattern.

If from block 10 comparison came. The signal O, then the trigger 13 remains in the initial state, and the signal from its inverse output permits the issuance of a combination of the output of the device and the recording of this combination into the second buffer

55

geers 19.1-} 9. (N-I) T. ,, ,, .., TI, depending on whether the coefficients G ,,,,, 6 ,, are equal to or not equal to zero

The control unit 6 operates as follows.

The state of the counter 20 at each time is the address for the memory block 21, In the memory block 21, the M-bit binary combinations are stored

The current register 12, and the signal from the direct output prohibits the issuance of a combination to the output of the device from the second buffer register 12 and overwriting this combination in the register.

If the I signal came from the comparison block 10, the flip-flop 13 is transferred to cocTOHirae when a logical signal 1 is present at its direct output. The signal from the direct output of the flip-flop 13 permits the issuing of a combination from the second buffer register 12 to the output of the device and the rewriting of the output combination to the register, On the signal from the inverse output, the combination of the first buffer register 1 to the output of the combination device and the rewriting of this combination are prohibited

in the second buffer 1 register register 12. Thus, the device does not receive the decoded code combination at the moment (it contains an incorrigible error combination), but

previous decoded without errors or with correctable error code combination.

The polynomial degree calculating unit 9 operates as follows.

From the arithmetic unit 4 to the input of block 9, the calculated coefficients of the error error are successively obtained. If the degree of a polynomial is

at t, t, e, the coefficient G of the polynomial O1chibok is not equal to zero, then trigger 19, NT is triggered. The logical 1 signal from its direct output goes to the decoder Ig, the signal from the inverse output of this trigger enters the I 17 elements, prohibiting the triggering of the I9, l-19 .. (Nl) Ti triggers,.,., Tt,, C a The output of these triggers to the decoder 18 receives a logical O signal. At the outputs of the decoder there is a signal corresponding to the binary number t.

If the coefficient is C. Oh, the signal from the inverse trigger output

  triggers trig

geers 19.1-} 9. (N-I) T. ,, ,, .., TI, depending on whether the coefficients G ,,,,, 6 ,, are equal to or not equal to zero

The control unit 6 operates as follows.

The state of the counter 20 at each time is the address for the memory block 21, In the memory block 21, M-bit binary combinations are stored

15

where M is the number of devices that need to be controlled. The output of each bit block. 1 memory is connected to, the input of the device, the operation of which g controls this bit of the memory block 21.

For example, the input of the calculator 3 syndromes from the control unit 6 should receive only one signal indicating at which point the registers I of the calculator 3 syndromes are zeroed. I Therefore, the calculator of 3 syndromes is connected -: it is occupied with only one discharge of the block 21 of the memory of the block 6 of the control. From the output of this bit, the input of the calculator of 3 syndromes is followed by zeroes during the n-1 cycles, and one on the n-th cycle, since the calculation of the syndromes ends on the n-th cycle, and after these syndromes are recorded in the arithmetic unit 4, the registers of the calculator syndromes must be reset to zero.

The arithmetic unit 4 is a much more complex device than the calculator of 3 syndromes, and more control signals are required for its operation. The number of control signals depends on the specific implementation; arithmetic unit 4, I Comparison block 10, mask-block 7 and error counter 8 for their work also require one control signal, therefore their control inputs are connected to the corresponding bits of the memory block 21 of the control block 6,. .

A metic block is the first, second, and third decoder inputs, respectively, characterized in that, in order to improve the noise immunity of the decoder, a masking block, an error counter, a comparator, a polynomial degree calculator, and a control block, whose input is connected to the second input, are entered into it. the first, second, third, fourth, and fifth outputs — with the third inputs of the calculator of the syndromes and the arithmetic unit, the first inputs 11 of the computing unit of the degree of the polynomial and the comparison unit, and the combined first inputs The error counter and the masking unit, respectively, the second input of the error counter are connected to the output of the polynomial memory unit, the output is connected to the second input of the comparison unit, the second input of the polynomial degree calculator is connected to the output of the arithmetic unit, the third input the comparison, the output of which is connected to the second input of the masking unit, the third and fourth inputs of which are connected respectively to the second input of the decoder and the output of the modulo two, the output of the masking unit is the output of the decoder.

20

thirty

Calculation block

; depending on the specific implementation, it may require several control signals.

Claims (4)

1. A linear code decoder containing successively connected buffer register and modulo-two adder and serially connected calculator of syndromes, an arithmetic unit and a polynomial memory block, the output of which is connected to the second input 2, the Decoder pop.1, which is different and that the control unit contains a serially connected counter and a memory block, the counter input is the device input, the outputs polynomial powers of 40 memory blocks — corresponding to the device outputs. 3. The decoder according to claim 1, that is, with the fact that the masking unit contains a trigger, elements 2I-Sh1I, The registers, the first and second inputs of the trigger are the first and second inputs of the masking unit respectively, the combined first inputs of the registers are the third input of the masking unit, the second input of the first register is the fourth input of the masking unit, the output of the first register is connected to the first inputs of elements 2I- OR, the output of the first element 2I-IPI 50 modulo two adder house, the first combined inputs / buffer register gg is connected to the second input of the second register and the calculator of syndromes, the second gistras, the output of which is connected to the combined input of the buffer register. the second inputs of the 2I-OR, pr-ra elements, the calculator of the syndromes and the block by the memory and inverse outputs of the trigger of the junction of the polynomials and the second input of the arithdineny, respectively, with the third and A metic block is the first, second, and third decoder inputs, respectively, characterized in that, in order to improve the noise immunity of the decoder, a masking block, an error counter, a comparator, a polynomial degree calculator, and a control block, whose input is connected to the second input, are entered into it. the first, second, third, fourth, and fifth outputs — with the third inputs of the calculator of the syndromes and the arithmetic unit, the first inputs 11 of the computing unit of the degree of the polynomial and the comparison unit, and the combined first inputs The error counter and the masking unit, respectively, the second input of the error counter are connected to the output of the polynomial memory unit, the output is connected to the second input of the comparison unit, the second input of the polynomial degree calculator is connected to the output of the arithmetic unit, the third input the comparison, the output of which is connected to the second input of the masking unit, the third and fourth inputs of which are connected respectively to the second input of the decoder and the output of the modulo two, the output of the masking unit is the output of the decoder. 71432786 the fourth inputs of the elements 2I-I.PI, the output of the second element 2I-IPI is the output of the masking unit. l p 4. The decoder of claim 1, of tl and h a yu and u with 5G in that the calculator of the degree of a polynomial contains groups of elements I, N triggers, where N is the degree of the error polynomial, and the decoder, the first inputs the elements of the first group and the combined first inputs of the flip-flops are the corresponding first inputs of the computing unit of the degree of the polynomial, the outputs of the first elements of the first group of the first group, except the last, are connected to the first inputs of the corresponding elements of AND § ig, 2 eight the second group, the outputs of which are connected to the second inputs of the corresponding triggers, except the last, the output of the last element And the first group is connected to the second input of the last trigger, the inverse outputs of the trigger, except the first, are connected to the corresponding inputs l- (il) (,,,., N) the elements of the second group, the second inverse inputs of the elements and the first group, respectively, are combined and are the second inputs of the calculator of the degree of the polynomial, the direct outputs of the flip-flops are connected to the corresponding inputs of the decoder are the outputs. L " 15 / 7 / f / zoo Y / j i / y fPue-J 18 Ha scheme compare , - / 5f / knots