SU911721A1 - Adaptive analogue-digital converter - Google Patents

Description

The invention relates to digital electrical measuring technology and is used in adaptive systems for collecting and transmitting digital measuring information.

An adaptive analog-to-digital converter is known, which contains the first and second comparison blocks, the first inputs of which are connected by themselves, the OR element, the timer, and the register, whose control inputs are connected to the timer input and the output of the OR element, the output of the first comparison block is connected to the first the input element OR, the output of the second comparison block is connected to the second input of the element OR, the first and second triggers, the first and second reversing pulse counters, the first and second converters code-analog, multiplexer, pulse generator owls, key, delay line, information outputs of the first reversible pulse counter are connected to the information inputs of the first converter-analogue and to the first group of multiplexer inputs, the output of the code-analog converter is connected to the second inlet of the first comparison unit, information outputs of the second reversible pulse counter are connected with the information inputs of the second code-analog converter and the second group of multiplexer inputs, the outputs of which are connected to the information inputs of the register, the output of the second The code analog counterpart is connected to the second input of the second comparison unit, the output of the first comparison unit is connected to the installation input zero of the first trigger and the first control input of the multiplexer, the output of the second comparison unit is connected to the installation input

15 units of the first trigger and the second control input of the multiplexer, the output of the pulse generator is connected to the information input of the key, the output of which is connected to the counting 20 inputs of the first and second reversible pulse counters, the control input of the key is connected to the inverse output of the second trigger, the installation input of the unit second trigger

25 is connected to the output of the delay line, the input of which is connected with the input of the zero setting of the second trigger and the output of the OR element; the control inputs of the direct count of both reversible pulse counters are connected

between each other and connected to the ijHBepcnogo output of the first flip-flop, and the control inputs of the countdown of both reversible pulse counters are interconnected and connected to the forward output of the first flip-flop 11.

The disadvantage of this converter is 5G. low efficiency coefficient of adaptive converter.,

 The purpose of the invention is to increase the coefficient. efficiency adaptive converter.

The goal is achieved by the fact that an adaptive analog-to-digital converter containing the first and second comparison blocks, the first inputs of which are connected to the input bus of the first and second triggers, is the lead line, the input of which is connected to the output of the first element OR, with the timer input, with the control the input of the first register and with the input - the zero setting of the second trigger, the installation input of the unit of which is connected to the output of the delay line ,. the first information input of the multiplexer is connected: with the output of the first reversing counter of the pulse, and. with the input of the first I converter, an analogue code whose output is connected to the second input of the first comparison unit, the second information input of the multiplexer is connected to the output of the second reversible pulse counter and to the input of the second, code analogue converter, the output of which is connected to the second (The input to the second comparison unit, the first control input of the multiplexer is connected to the output of the first comparison unit, to the first input of the first OR element, and to the installation input zero of the first trigger, the second control input of the multiplexer not with the output of the second comparison unit, with the BTOpbW input of the first OR element of the OR and with the input of the unit of the first trigger, the control input of the first key. Connected with the inverse output of the second trigger, and the information input with the generator output — pulses; the multiplexer output is connected the information input of the first register, the second and third registers of the first, second, third and fourth elements AND, the second element OR, the second key, the inverter, the subtraction unit, the division block, the comparison block and the pulse counter, and the pulse the first input of the first AND element is connected to a direct output of the first flip-flop inverse output is connected to a first input of the second AND gate, .vtoroy input coupled to an invariant population-inverted output of the second flip-flop and

with the second input of the first element and the output of which is connected to the first and control inputs of the reverse: the accounts of the first and second. reversible pulse counters, the first control inputs of the direct counting of which are connected to the output of the second element and the second control 1 -. inputs countdown. - with the release of the third element and the second control inputs of the forward

f accounts - with the output of the fourth element I, the first input of which is connected to the sign output of the subtraction unit and through an inverter with the first input of the third element I, the second input of which is connected to the second input of the Fourth element and, with the direct output of the second trigger. The second key, the output of which is connected to the first input of the second, element OR, the second input of which is connected to the output of the first key, and the output to the counting inputs of the first and second reversing pulses, the information input of the second register is connected to the output The first register and the first input of the subtractor, the second input of which is connected to the output of the second register, the control input of which is connected to the control input of the third register and to the output of the first OR element, the code of the subtractor is connected to the first input of the division unit, the second input of which connected to the output of the third register, the information input of which is connected to

timer output, the output of the block division. connecting with the first-input of the code comparison block, the second input of which is connected to the output of the pulse counter, the counting input of which is connected to the output of the pulse generator, the first control input-to the output of the delay line, the control input unit to the output of the code comparison block and with the information input of the second key.

FIG. 1 shows the functional diagram of an adaptive, analog-digital converter; in fig. 2 is a diagram explaining his work.

The converter (Fig. 1) contains the first trigger 1, the first, the second third, and the fourth element AND 2, 3, 4, and 5, respectively, the inverter 6, the first element OR 7, the first and second blocks 8 and 9 of the comparison, the first

Claims (1)

 and second converters 10 and 11 code-analog, first and second reversible counters 12 and 13 pulses, multiplexer 14, first and second registers 15 and 16, second element OR 17, subtraction unit 18, pulse generator 19, first key 20, timer 21, the third register 22, the second trigger 23, the delay line 24, the second key 25, the division block 26, the code comparison block 27 and the pulse counter 28. Converter - works as follows. In the initial state, the second three ger .23. set in the zero state, in the reversible counters 12 and 13 are set. the values corresponding to the values of the output signals of the code-analogue converters 10 and 11 (-.) and (-e), where the admissible value of the difference of convertible Ux and approximations tsego or ipkAz. Ignalov. When the control key of the first key 20 is turned on, the voltage of the logical unit is applied, the key 20 is opened and the pulses of the generator 19 start to flow through, the first key 20 and the second element I OR 17 to the estimated input of the reversible counters 12 and 13 impulses owls At the same time, the first control inputs of the direct counting of reversible counters of 12 and 13 pulses through the second element I 3 are supplied with the voltage of the logical unit from the inverted output of the first trigger 1, if and X JТЖА f when Ch. .Fi2 is first control QDDs of the counting input through the first element L 2-is supplied - the voltage of the logical unit from the direct output of the first trigger -1. The contents of both reversal counters 12 and 13 change until the sign of the inequality between the value of Uv and UDKAO changes. the instant of time (Fig. 2), when Uit exceeds the value UnxKf 2C, a comparison pulse is generated at the output of the first block. A pulse confirms the state of the first trigger 1 and, entering the first control input multiplexer 14, connects the output of the first reversible counter 12 pulses through multiplexer 14 to the information input of the first register 15, This pulse, passing through the first element OR 7, confirms the state of the second trigger 23. records in the first register 15 a code fixed by the first reversible counter 12. pulses, and enters the inputs of the expander line 24 and timer 21., Timer 21 measures the time intervals between the pulses at the output of the first, & ORENT 7, the pulse from the output of delay line 24 delayed by the time interval tr sets The second trigger 23 is in the state of unity, and the pulse counter 28 is in zero sequence. The T-switch time is selected, -from the condition that at a known pulse frequency f from the generator 19, the state of both reversible counters 12 and 13. pulses changed in time f by value, corresponding to modifying the output signals of both converters, the code analog 10 and 11 by the value of 6. Starting from the moment of time about, the converter monitors. following a change in the converted signal, i.e., always executed. inequalities UnKAv; SUx (t) 5. At the moment of setting this inequality, the information from the first register 15 is rewritten into the second register 16, and from timer 21. into the third register 22, the subtraction unit 18 determines the difference n of the values recorded in registers 15 and 16, and the division unit 26 calculates the value m | n, where m is the value fixed by the timer, at the moments of time when the state of the pulse counter 28 coincides with the output code of the division block 26, the output of the block -27 of code comparison, the pulse appears, which sets the pulse counter 28 zero state, and through an open second minutes key 25 and the second OR gate 17 is supplied to the counting inputs of the reversible counters 12 and 13 pulses. In this case, the module of the slope of the output signals of both transducers of the codecs will be equal to. the module of the average steepness of the converted signal in the previous conversion cycle The coincidence of the Sjj values is provided by connecting the sign output of the subtraction unit 18 through the inverter 6 and the third element I 4 and through the fourth element I 5 to the second control inputs of the reverse and two counters of the two reversible counters respectively 12 and 13 pulses. When changing, the inequality sign Uy 7 / OpkAi - FIG. 2) the second block 9 compares, the first trigger I is set to the logical one state, the second trigger 23 to the logical zero state, the first key 20 is opened and the pulses from the generator 19 pass through the first key 20 to the counting inputs, reversible counters 12 and 13. pulses, reducing their content. At time t - t, the second trigger 23 is set to the state of the logical unit, the first key 20 is closed, and the second key 25 opens. And the pulses from the output of the code comparison unit 27 are sent to the counting inputs of the reversible counters 12 and. 13 pulses. At the same time, the logical zero output voltage f (since the change in U during the 1st cycle is negative) appears at the sign output of the subtraction unit to the second control inputs of the reverse counting of the reversible counters, the voltage of the logical unit, and the steepness of the output signals / transducers the analogue code from the moment C- + f is equal to the average steepness of the signal to be converted over the time interval (t.-f, t;}. Starting from the moment when Ux becomes equal to one of the signals. or OCA, the operation of the converter is repeated. Since The cc signals of cp are the first-order polynomials, the adaptive analog-to-digital conversion efficiency, defined as the ratio of the number of samples taken over time, with the approximate polynomial zero in number to number of samples over time an approximate first-order polynomial, greater than one and, therefore, adaptive transformation is more efficient. Formula of the Invention An adaptive analog-to-digital converter containing first and second blocks as compared and, the first inputs of which are connected to the input bus, the first and second triggers, a delay line, whose input is connected to the output of the first OR element, to the timer input, to the control input of the first register and to the input of the second zero trigger setup, unit input which is connected to the output of the delay line, a multiplexer, the first information input of which is connected to the output of the first reversible pulse counter and the input of the first converter — an analogue, the output of which is connected to the second input of the first comparison unit, second information input of the multiplexer is connected to the output of the second reversible pulse counter and to the input of the second converter code. An analogue, the output of which is connected to the second input of the second comparison unit, the first control input of the multiplexer is connected to the output of the first comparison unit the first element OR and the installation input. The first trigger, the second control input of the multiplexer is connected to the output of the second comparison unit, with the second input of the first OR element and to the installation input of the unit of the first The control input of the first key is connected to the inverse output of the second trigger, and the information input to the output of the pulse generator, the output of the multiplexer is connected to the information input of the first register, in order to increase the efficiency coefficient of the adaptive transducer to it the second and third registers are entered, the first, second, third and fourth elements are AND, the second element is OR, the second key, the inverter, the subtraction unit, the division unit, the code comparison unit and the pulse counter, the first input of the first element nta AND is connected to the direct output of the first trigger, the inverse output of which is connected to the first input of the second element And, the second input of which is connected to the inverse output of the second trigger and to the second input of the first element And whose output is connected to the first and reverse control inputs the first and second reversible pulse counters, the first control inputs of the direct counting of which are connected to the output of the second element And, the second control inputs of the counting back to the output of the third element And, and the second control inputs of The first account is connected to the sign output of the subtraction unit and through an inverter to the first input of the third element And whose second input is connected to the second input of the fourth element And, to the direct output of the second trigger and to the control input The second key, the output of which is connected to the first input of the second OR element, the second input of which is connected to the output of the first key, and the output to the counting inputs of the first and second reversible pulse counters, the information input of the second register A is connected to the output of the first register and to the first input of the subtraction unit, the second input of which is connected to the output of the second register, the control input of which is connected to the control input of the third register and, to the output of the first OR element, the output of the subtraction unit division, the second input of which is connected to the output of the third register, information input KbTopo.ro is connected to the output of the timer, the output of the division block is connected to the first input of the code comparison block, the second input of which is connected to the output of the pulse counter The main control input is connected to the output of the delay line, the second control input is connected to the output of the code comparison unit and to the information input of the second key. Sources of information taken into account at the time of the expert examination 1. USSR Author's Certificate for the application 2775438 / 18-21, cl. H 03 K 13/02, 1979 (prototype). Fug.