SU1508348A1 - Code-to-voltage converter - Google Patents

Abstract

The invention relates to automation and computing and can be used in digital-analog and analog-digital converters of information. The purpose of the invention is to increase speed. Converter code - voltage contains register 1, computing device 2, converter 3 code-time interval, shaper 4 pulse sequences, 5 pulse generator, RS flip-flop 6, element 7, pulse counter 8, reference source 9, three keys 10-12, an analog storage device 13, an integrator 14, a comparator 15, a short pulse shaper 16 and a delay element 17. Computing device 2 is performed on a code multiplier, a code adder and two code inverters. The introduction of the computing device 2, the pulse counter 8 and other elements with corresponding connections allows to increase the speed of the converter by reducing the time of the transition process of setting the output signal when the input code is changed to one conversion cycle. 1 hp f-ly, 3 ill.

Description

31508

The invention relates to automation and computing and can be used in digital-analog and analog-digital converters of information.

The purpose of the invention is to increase the speed.

FIG. 1 shows the functional diagram of the converter code-voltage; in fig. 2 - functional diagram of the computing device; in fig. 3 is a diagram explaining the operation of the converter.

Converter code - voltage (Fig. 1) contains register 1, computing device 2, converter 3 code - time interval, generator of 4 pulse sequences, generator of 5 pulses, RS-flip-flop 6, element 7, pulse counter 8 a reference voltage source 9, three switches 10-12, an analog storage device 13, an integrator 14, a comparator 15, a short pulse shaper 16, and a delay element 17. The computing device (figure 2) is performed on the multiplier 18 codes, the adder 19 codes and two inverters 20 and 21 codes.

Converter code - voltage works as follows.

In the initial state, integrator 14 is zero, converter 3 code - time interval is blocked, RS-flip-flop 6 is in zero state, blocking And 7 element.

At time t, (Fig. 3., diagram A), the pulse from the first output of the pulse generator 4 converts the code into the register 1, the short-circuit flip-flop 6 is set to one, and the pulse counter 8 is zeroed. Signal level log. 1 from the output of the KZ-flip-flop opens element I 7, through which the pulses of the generator 5 arrive at the synchronization input of the counter 8 and mycoles. The output signal of the RS-flip-flop 6 closes the key 11 through which the voltage of the source 9 of the reference voltage enters the non-inverting input of the integrator 14. As a result, at the output of the integrator 14, the voltage starts to increase. When the output voltage of the integrator 14 is reached, the value E, equal to the voltage of the source 9 of the reference voltage, triggers the comparator 15,

Q

5 0 5 0

five

ABOUT

0

five

the output signal of the RS-flip-flop 6 is transferred to the zero state, and the postproduction of pulses from the generator 5 to the input of the counter 8 stops; N, -NN, / Nj), where N, is the nominal value of the code to be converted; N is the current value of the code being converted; N is the code at the output of the counter 8. The moment in time t is the end of the first conversion cycle and the beginning of the second.

At time t, the second output of the driver 4 generates a start-up signal for the converter 3 code-time interval and at its output forms the leading edge of the measuring time interval, the duration of which is proportional to the code N. The leading edge of the measuring pulse closes the switch 10 and the inverting input of the integrator 14, the voltage E comes from the output of the source 9 of the reference voltage. The voltage at the output of the integrator 14 begins to decrease, as a result of which the compressor 15 returns to its original state. At the end of the measuring pulse, a voltage of -1 kEdt is detected at the output of the integrator 14. The falling edge is measuring

The first pulse is started by the short pulse shaper 16, by means of which the output voltage of the integrator through the key 12 is entered into the analog storage device 13. The pulse 16 of the pulse delayed by means of the delay element 17, the integrator 14 is zeroed out. At this time, the second conversion cycle ends, a voltage is generated at the output of the converter, proportional to the code being transformed, and the device is ready for the next conversion cycle.

Computing device 2 (FIG. 2) is intended to form the code N. The multiplication of two n bits of the N and NJ codes is performed by a factor of 18 codes, the higher n bits of the multiplication result are summed with the corresponding bits of the Nj code (inverted by the inverter 20 codes ) using the adder 19 codes. The result of the summation after the inversion

15

 .1508348

Inverter 21 is fed to

input of the calculating device 2. An exception when summing the low bits of the code at the output of the multiplier 18. The codes are equivalent to the operation of dividing the result by N.

Transducer 3 code - time interval can be implemented on a pulse counter that has inputs for storing the initial code. Shaper 4 is a clocked generator that is synchronized by the output pulse of the comparator 15. With the same delay, the same pulse of the comparator is triggered by the waiting multivibrator, the output pulse of which triggers the converter 3, the code-time interval.

The algorithm of computing device 20 can be explained using diagrams (Fig. 3). Let the nominal value of the transfer coefficient of the integrator 14 and the frequency of the generator of 5 pulses correspond to the diagram A, then 25 (,) / f, E (t -tp / f, U ,,,,, Taking into account that the interval (,) is proportional to the nominal value of the converted code N, and the output voltage is proportional to the current value of the code Nj, we get

Ni

out

(one)

When changing the transfer coefficient of the integrator 14 (Fig. 3, diagram B), we write

(t, -t,) / foE (t4-t,), x, whence

Nj / E (N3-N,) / UB ,,,, (2)

and when changing the frequency of the pulses of the generator 5 (Fig. 3, chart B)

(t7-tg) / (fo + uf) E (tq-te) / (+

+ bf) UBbu,

or ,

Nj / E (N, -N4) / uU- (3)

Substituting (1) into (2) and (3) and putting UB ,,), Ueb, x, we get

N, N,. (4)

 Thus, the obtained algorithm (4) of the computing device 2 ensures that the output nagging of the converter is proportional to the code — the voltage to the value of the converted code Nj at slower measurements, the transfer coefficient of the integrator 14, or the frequency of pulses.helepaTopa 5. Moreover , when it changes

15

348

.

p 20 25 about

45

with

40

50

the value of the converted code N the steady state value of the output signal is provided in one conversion cycle.

Claims (2)

1. Converter code — voltage that contains a source of reference voltage, the output of which through the first switch is connected to the inverting input of the integrator, the output of which through the second switch is connected to the input of an analog storage device, the output of which is the output bus, the non-inverting input of the integrator is connected to the output of the third key, the control input of the first key is connected to the output of the converter code — a time interval, characterized in that, in order to increase speed, a register is entered into it, calculate device, comparator, pulse counter, pulse generator, RS trigger, pulse shaper, AND element, delay element and short pulse shaper, whose input is combined with the control input of the first key, and the output connected to the control input of the second key and through the delay element is connected to the integrator zeroing input, the output of which is connected to the first input of the comparator, the second input of which is connected to the output of the reference voltage source and the information input of the third key, The comparator output is connected to the input of the RS-trigger setting to the zero state and to the control input of the pulse trainer, the first output of which is connected to the zeroing input of the pulse counter, the RS-trigger setting input and the register write enable The information inputs of which are the input bus and the outputs are connected to the corresponding first inputs of the computing device, the second inputs of which are connected to the corresponding outputs of the pulse counter, and the outputs Ina with corresponding information inputs of the code-time converter, the start input of which is connected to the second output of the pulse trainer, and the clock input is combined with the first input of the And element and connected to the output of the pulse generator, the output of the And element is connected to the counting input of the pulse counter, the second input element And is combined with the control input of the third key and is connected to the output of the RS flip-flop. 2. The converter according to claim 1, T is characterized in that the computing device is performed on a code multiplier, a code adder, the first and second blocks of inverters, the outputs of the last of which are the corresponding outputs of the computing device, and the inputs are connected to the corresponding outputs of the code adder, the first time and the second inputs of which are CONNECTED to the corresponding outputs of the first inverter unit and the corresponding outputs of the code multiplier, the first inputs of which are combined with the corresponding inputs of the first inverter unit and are the first inputs of the computing device, The second inputs of the code multiplier are the second inputs of the computing device. (rig 2  tih ti ts ieir te ff    I I I I I I I I I I I D I I t I U .J /