SU907861A1 - Device for receiving information in frequency code - Google Patents

Description

(54) DEVICE FOR RECEPTION OF INFORMATION IN FREQUENCY CODE

one

The invention relates to telecommunications and can be used in systems with frequency encoding of messages.

A device for receiving information in the frequency code is known, comprising a series-connected selective amplifier, a notch filter and a first phase shifter, an adder, the output of which is connected to the clock generator and the input of the time delay block through the null organ, the other the input of which is connected to the output of the counter connected to another input of the notch filterJpa 1.

However, in the known device, the reception speed is insufficient.

The purpose of the invention is to increase the reception speed.

To achieve this goal, a device for receiving information in the frequency code, containing a series-connected selective amplifier, a notch filter and a first phase shifter, an adder, the output of which is connected to the clock generator and the input of a time delay through a null organ. the input of the key, another input of which is connected to the output of the counter connected to another input of the notch filter, the first and second multipliers, the second phase shifter, the threshold block and the spread are entered the divider, the output of the selective amplifier is connected to one input of the first multiplier and through the second phase shifter to one input of the second multiplier, another input of the multiplier is connected to the output of the first phase shifter, the output of which is connected to the counter input through a threshold unit, the other inputs of which are connected to the output of a clock generator through a distributor.

The drawing shows a structural electrical circuit of the proposed device.

Claims (2)

The device contains a selective amplifier 1, notch filter 2, null organ 3, time delay block 4, switch 5, generator 6 clock pulses, phase shifters 7 and 8, multipliers 9 and 10, adder 11, threshold block 12, counter 13, distributor 14 The device works as follows. The received signal through the selective amplifier 1 is fed to the input of the notch filter 2. At the beginning of the send, the distributor 14 connects to the output of the threshold unit 12 the most significant bit of the counter 13 and sets this bit to one. Since the remaining bits of the counter 13 are previously reset, the notch filter 2 is tuned to the average frequency of the received code. The determination of the frequency of the received signal is carried out in stages. At the first stage, a comparison is made with the average frequency of the frequency code. At each stage, there are three possible options: the frequency of the received signal coincides with the pole of the notch filter 2, the frequency of the received signal above the pole of the notch filter 2, the frequency of the received signal below the pole of the notch filter 2. When the notch frequency coincides with the frequency of the received signal, then the notch output filter 2 through Vits zero signal, which through multipliers 9 and 10 and the adder 11 is fed to the input of the zero-body 3, which stops the generator 6 clock pulses and starts block 4. After ii regulated time set unit 4, the information output from the counter 13 through the switch 5 is provided require Yeh-lii. If the frequency of the received signal does not correspond to the pole of the notch filter 2, then as a result of multiplying the output signal of filter 2 with the input shifted by 90 °, as well as multiplying the output signal of the notch filter 2 shifted by 90 ° with the input, followed by summing up, The adder 11 receives a signal in the form of a constant voltage, the polarity of which is determined by the difference between the frequency of the received signal and the notch filter frequency. 2. If the frequency of the received signal is higher than the notch pole, then the voltage at the output of the adder 11 is positive, otherwise it is negative. Since the circuits of phase shifters, multipliers, and adder are wide-band, the determination of the sign of the frequency difference occurs almost instantly. From the output of the adder 11, the signal enters the threshold unit 12 with a fixed positive threshold level. If the frequency of the received signal is higher than the pole of the notch filter 2, then the output of the adder 11 is positive voltage, which exceeds the threshold of the threshold unit 12, which in turn resets the high discharge of the counter 13. If the frequency of the received signal is lower than the pole of the notch filter 2, This voltage at the output of the adder 11 is negative and below the threshold of the threshold unit 12. In this case, the high bit of the counter 13 remains set. In the next cycle, the distributor 14 connects to the output of the threshold unit 12 the next discharge of the counter 13 and sets it to one. Further rearrangement is similar. As a result of the restructuring in the counter 13 will be recorded a number corresponding to the received frequency. The maximum number of tuning operations is equal to Iog2 N (N is the number of positions of the received frequency), while the known device requires N operations. The advantages of the proposed device as compared with the known ones depend on the code base. When using a 16-digit code, the speed of finding the frequency increases by 4 times, which leads to an increase in the effective speed of 1.5-2 times with constant noise immunity. The invention The device for receiving information. In the frequency code, containing a series-connected selective amplifier, notch filter and the first phase shifter, the adder, the output of which through a nullorgan is connected to the input of the clock generator and the input of the time delay block, the output of which is connected to one key input, the other the input of which is connected to the output of the counter, which is connected to another input of the notch filter, characterized in that, in order to increase the reception speed, the first and second variables are introduced the inhabitants, the second phase shifter, the threshold unit and the distributor, the output of the selective amplifier is connected to one input of the first multiplier and through the second phase shifter to one input of the second multiplier, another input of the multiplier is connected to the output of the first phase shifter, another input of the second multiplier is connected to the output of the notch filter, the outputs of both multipliers are connected to the inputs of an adder, the output of which is connected to the input of a counter through a threshold unit, the other inputs of which are connected through a distributor s with the output of the clock generator. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 657658, cl. H 04 L 27/26, 1977 (prototype).