SU903876A1

SU903876A1 - Device for distributing tasks

Info

Publication number: SU903876A1
Application number: SU802913503A
Authority: SU
Inventors: Анатолий Хатынович Ганитулин; Сергей Игоревич Шматков
Priority date: 1980-02-06
Filing date: 1980-02-06
Publication date: 1982-02-07

Description

(54) УСТРОЙСТВО ДЛЯ РАСПРЕДЕЛЕНИЯ ЗАДАНИЙ(54) DEVICE FOR JOB DISTRIBUTION

II

Изобретение относитс к вычислительной технике, в частности к устройствам распределени заданий (задач ) в вьмислительной системе.The invention relates to computing technology, in particular, to devices for distributing tasks (tasks) in the hyperthin system.

Известно устройство обмена, которое содержит линейный блок, блок управлени поиском, и обменом, счетчик номера абонента, дешифратор поиска готовности, дешифратор управлени обменом, регистр готовностей абонентов, сборку сигналов требований обмена. В устройстве анализируетс готовность абонентов к обмену и организуетс обмен выбранного абонента с ЦВМ )3 .There is an exchange device that contains a linear unit, a search and exchange control unit, a subscriber number counter, a readiness search decoder, an exchange control decoder, a subscriber readiness register, an assembly of exchange request signals. The device analyzes subscriber readiness for the exchange and organizes the exchange of the selected subscriber with a digital computer 3.

Недостатками устройства вл ютс низкое быстродействие и тот факт, что устройство,не позвол ет организовать одновременный обмен с несколь кими свободными абонентами.The drawbacks of the device are the low speed and the fact that the device does not allow simultaneous exchange with several free subscribers.

Ь)аиболее близким к предлагаемому по технической сущности вл етс устройство дл распределени задани процессорам, содержащее блок управлени поиском и распределением к первому входу которого подключен выход элемента ИЛИ окончани распределени . Ко второму входу блока управлени поиском и распределением подсоединены выходы регистра готовностей процессоров, а к третьему входу - шины необходимого числа процессоров. Первый выход блока управлени подсоединен к входу, управ10 л юпхему приемом кода из шин в регистр со сдвигом, второй выход подсоединен к входу, управл ющему сдвигом в регистре со сдвигом. Третий выход блока уп.равлени подсоединен B) the closest to the proposed technical entity is a device for distributing a task to the processors, containing a search and distribution control unit to the first input of which the output of the element OR is connected to the distribution end. The outputs of the processor readiness register are connected to the second input of the search and distribution control unit, and the required number of processors are connected to the third input. The first output of the control unit is connected to the input, the control unit receives the code from the bus into the register with offset, the second output is connected to the input that controls the shift in the register with offset. The third output of the control unit is connected

Claims

15 to the bus refusal to assign the task. The outputs of the register with the shift are connected to the inputs of the element OR the termination of the distribution and to the first inputs of the elements AND of each of the n (by the number of processors) groups. The corresponding inputs of the readiness register are connected to the second inputs of each group of elements. To third one inputs. elements 5 are connected to the bus numbers of the task (task), to the outputs of each group of elements and connected the inputs of the corresponding elements OR, the outputs of which are connected to the zero inputs of the corresponding tr. register register shift and readiness register. The inputs of the corresponding groups of elements I are connected to the input 5 of the processors, and the outputs of the processor 7 are connected to the single inputs of the trigger register 21. The drawback of the device is the impossibility of using natural redundancy for duplicating the execution of tasks. The purpose of the invention is to enhance the functionality by using natural redundancy to duplicate the execution of tasks. The goal is achieved. the fact that in the device for assignments containing the control unit, the shift register, the first element OR, the first group of elements OR, the register of readiness, the first group of elements AND, the first inputs of the elements AND of the first group are connected to the corresponding outputs of registers, the inputs of which are connected to the inputs of readiness of the main processors of the device, the outputs of the register of readiness are connected to the inputs of the code of the free processors of the control unit, the failure output of which is connected to the output of the failure of the device, the inputs of the code la required about tsessorov are connected to the inputs of potentiometers infor shift register and, with the code number of inputs required processor control unit, outputs regibtra shift. - with the second inputs of the elements of the first group and with the first group of inputs of the first element I-irHi, the output of which is connected to the input of the distribution end of the control unit, the output of the shift control of which is connected to the input of the shift control of the shift register, the reset inputs of which are connected to the first inputs reset register readiness and. to the outputs of the IL elements of the first group, the inputs of which are connected to the outputs of the corresponding I AND elements of the first group and to the outputs of the number of the main task of the device. 9 4 third inputs of elements AND of the first group are connected to the inputs of the code of the device job number, the duplication register, the second group of OR elements, the third group of OR elements are entered. the register of removal, the second element OR, the third element SHS, the fourth element OR, the additional shift register, the second group of elements AND, the third group of elements AND, the outputs of which are connected to the corresponding inputs of the elements OR of the third group and to the corresponding outputs of the number of the device to be removed, readiness duplicate processors. The device is connected to the information input of the redundancy register, the outputs of which are connected to the first inputs of the elements of the third group and to the code inputs of the processors occupied by the duplication of the control unit, the output of the shift control of the removal register of which is connected to the control input. ki shift register removal, the outputs of which are connected to the second input. elements of the third group and with the inputs of the fourth element OR, the output of which is connected to the input of the removal end of the control unit, the output ends of the formation of the removal code of which is connected to the third inputs of the elements AND of the third group, the fourth inputs of which are connected to the inputs of the device’s job number, the inputs of the second element OR to the first inputs of elements AND of the second group, the second inputs of which are connected to the outputs of the register of readiness, and the third outputs - with the second inputs of the second group of inputs of the first element SH and with the input mi additional shift register data inputs are connected to the inputs of a code number necessary device processors vyho: rows of the second group of AND gates connected to the outputs of duplicated numbers specifying device and to the inputs of the second group IL11 elements whose outputs. connected to the second inputs of the reset register readiness j inputs installation register d. y and with the reset inputs of the additional shift register, input y. The receiving control of which is connected to the output of receiving control of the additional shift register of the control unit and the first input of the third OR element, the second input of which is connected to the output of receiving control of the shift register, the output of the third CMM element is connected to the input of receiving control of the shift register, the shift control input of the additional shift register is connected to the shift control output of the control unit, the input of the reference number of which is connected to the output of the second element OR, and the output of the sequential input - from the input Oms of sequential input of the register of removal, the reset inputs of which are connected to the inputs of zeroing of the register of duplication, the installation inputs of the register of readiness and the outputs of the third group of elements SH. In addition, the control unit contains two generators of single pulses, four triggers, the first, second, third and fourth group of elements AND, the first, second, third and fourth group of delay elements, the first and second registers, first, second, third and fourth three comparison schemes for more, a group of comparison elements for equality, two NOT elements, seven NEC elements, nine AND elements, a delay element, a pulse generator, the output of which is connected to the second input of the seventh AND element and to the first input of the eighth ale And the output of which is connected to the block shift control output and to the zero input of the third trigger, the direct output of which is connected to the second input of the ninth And element, the first input of which is connected to the output of the first HE element and to the zero input of the second trigger, direct output which is connected to the output of the end of the formation of the code removal code and to the first input of the seventh. Element And, the output of which is connected to the second input of the seventh element SH, the first input of which is connected to the input JBTOporo of the delay element and to the output of the fifth element SH, the inputs of which are connected to the outputs of the fourth group of elements And, the first input of the first element And the fourth group is connected to the output the second generator of single pulses and the input of the first delay element of the fourth group, the output of each q-ro delay element of the fourth group (, 2 ,. . . -1 where t. the number of processors in the processor unit) is connected to the first input q + l of the delay element of the same group and to the first input q + l of the fourth AND element of the fourth group, the output (tl) -ro of the delay element of the fourth group is connected to the input of the first delay element whose output connected to the single input of the third trigger and the single input of the second trigger, the second inputs of the fourth group of elements AND are connected to the outputs of the equality comparison element group, the first inputs of which are connected to the outputs of the second register, and the second inputs - to the outputs of the first register, information inputs of which are connected to the code inputs of the number of necessary processors of the control unit and to the second inputs of the first | Element Group I, the first input of the first Element AND of the first group is connected to the output of the first single pulse generator, to the input of the first delay element of the first group, to the input the first delay element of the second group and the first INPUT of the first element AND the second group, each i-th delay element of the first group (, 2 ,. . . , C), except {th. connected to the first input (i + l) -ro of the element I of the first group and to the input of (t + l) -ro a delay element of the same group, the output of the E-th delay element of the first group is connected to the control input of the fourth counter, the outputs of the first the groups of elements AND are connected to the inputs of the first element OR, whose output is connected to the installation input of the fourth counter, the outputs of which are connected to the first inputs of the second comparison circuit by more, the second inputs of which are connected to the second inputs of the third schema1, 1 comparison more and the outputs of the second counter, entrance mustache Installations of which are connected to the output of the second OR element, the input of the third delay element, the single input of the second register and the second input of the third OR element, whose inputs are connected to the outputs of the second group of AND elements. The first inputs of this group are connected to the code inputs of the number of free processors of the unit ; th j-ro delay element of the second group (, 2, i. . , -tl) is connected to the input (j + l) -ro of the delay element of the same group and to the second input (j + l) -ro of the element AND of the second group, the output (-l) -ro of the element delay 1 "and the second group is connected to the first input of the first element And the third group and with the input of the first delay element of the third group, the output of each K-th element-delay of the third group (, 2 ,. . . , / 2-1). connected to the first input of each (K + 1) -th element AND of the third group, the second inputs of the third group of AND elements are connected to the code inputs of the number of processors occupied by duplication, and the outputs to the first input of the third OR element, whose output is connected to the installation input third counter, output (-t. / 2-l) -ro delay element third. The group is connected to the input of the fourth element of the Zanderlski, the output of which is connected to the single input of the first trigger, the direct output of which is connected to the second inputs of the first and second elements of the Ink to the third inputs of the third, fourth, and fifth. the sixth elements AND, the output of the fourth element OR is connected to the reset input of the first, second, third and fourth counters, the first, second and third registers and to the left input of the first trigger, the first input of the fourth element OR is connected to the output of the control unit failure and to the output The first element AND the first input of which is connected to the output of the first comparison circuit on a larger one and with the first input of the second element AND, the output of which is connected to the first input of the third element And and the first input of the fourth element And the output of which is connected not with the second input of the eighth OR element, control output — reception of an additional block shift register and second input of the fourth OR element, the third input of which is connected to the output control of the reception of the shift register of the block and the output of the sixth SHS element, the first input of which is connected. to the output-p of the element I and the input of the second generator of single pulses, the second input of the sixth element SH) is connected to the first input of the eighth element OR, and to the output of the sixth element AND, the first input of which. connected to the output of the third element And, the first input of the fifth element And and the first input of the sixth element And, the second input of which is connected to the second input of the fifth e 6. . And 8 and the output of the third comparison circuit by more, the first input of which is connected to the output of the first counter and the first input of the first comparison circuit on more, the second input of which is connected to the output of the third counter, the output of the second comparison circuit is more connected to the second input of the third element And the second input of the fourth element And, the output of the second, delay element connected to the output of the sequential block input, the input of the first element is NOT connected to the input of the block removal end, the input of the second element is NOT connected to the input ok The distribution of the block and the output are to the zero input of the fourth trigger, the single input of which is connected to the output of the eighth element of the CMM, the third input of which is connected to the output of the ninth element And, the direct output of the fourth trigger is connected to the second inlet of the eighth element And, the output of the seventh element CM is connected to the output of the shift control of the block, the input of the first generator of single pulses is connected to the input of the block reference number. FIG. 1 and 2 shows a block diagram of the device. The device contains a control unit 1, a readiness register 2, a first CMM 3 distribution end element, a shift register 4, the first, second and third groups of elements AND 5, the first, second and third groups of elements OR 6, processors 7, tires 8 of the required number of processors, bus 9 job numbers, bus 10 failure, register 11 removal, shift register 12, backup register 13, start element RM 14, third reception element SH 15, fourth end removal command 16, replacement 17-19, registers 20 and 21, even -22 with shift chains, circuits 23, comparison by more, one time group of the equal comparison circuits 24, triggers 25-28, first, second and third groups of elements AND 29-31, elements AND 32-37, fourth group of elements And 38, elements And 39 and 40, elements, ШШ 41-43, first and the second elements NOT, the first, the second and third groups of delay elements 50-52, the delay elements 53 and 54, the fourth group of delay elements 55, the delay elements 56 and 57, the first and second generators 58 |, single pulses, the generator 59 pulses , the first 60, the second 61 outputs of the control unit 1, the first 62 input of the control unit 1, the third 63, the fourth 64 outputs of the control unit i , The second 65, the third 66, the fourth 67, the fifth 68 inputs of the block. 1 control, fifth 69, sixth 70, seventh 71 outputs of control unit 1, sixth 72 inputs of control unit 1. The proposed device operates as follows. According to buses 9, the job number, the code, the job number, is fed to the inputs of the OR 14 Run, the output of which generates a signal that controls the start of the first generator 58 of single pulses. At the same time, the required number of processors the number of processors arrives at the second inputs of the group of elements And 29 and on. single inputs of register 20 The code of the number of free processors from the readiness register 2 is fed to the second inputs of the second group of elements I 30, and the code of the number of processors occupied by duplication from the duplicate register I3 to the second inputs of the elements 31 A pulse from the output of the generator 58 delayed in the first group of delay elements 50, permits the sequential passage / generation of code units of the required number of processors through elements 29, each one from the entry of the corresponding elements 11 of the third group through a 27sh 41 element od counter 17 and to the input of the counter 22. As a result of polling, the pulse from the output of the generator 58 of all elements AND 29 in counter 17 generates the binary code of the required number of processors (n,), in register 20 — the received one-position code of the required number of processors, which is a set of units in succession dah register 20, and in c4etchchik 22 with shift chains - a binary code, doubled the required number of processors (2n "). Doubling the number of the required number of processors is obtained by shifting the contents of counter 22 left pulse received 610 from the last element 50 of the delay on the shift input of the counter 22. The pulse from the output 1 of the generator 58 single pulses, delayed by. delay elements 51 also allows sequential passage of code units of the number of free processors through an AND 30 group of elements; Each unit from the output of the corresponding AND 30 group of elements is fed through an OR 42 element to the input of the counter 18 and to the input that controls the shift of the register 21, shifting to the right of the contents of the register, which ensures the release of the high bit to receive the next unit of the code of the number of free processors through the delay element 54. In addition, the unit goes through the CMM element 43 on stroke counter 19. As a result, a binary code of the number of free processors (P (. ), and in register 21, a single-position code representing a set of units, the number of which is equal to the number of free processors. The pulse from the output of the last delay element 51 of the group, delayed by the delay elements 52, of the group permits the sequential passage of code units of the number of processors occupied by duplication through elements 31. groups. Each unit from the output of the corresponding element AND 31 of the group enters through the element OR 43 to the input of counter 19, thereby forming the binary code of the sum of the number of free processors and the number of processors occupied by duplication (). The signal from the output of the last delay element 52 is delayed by the delay element 53 The delay time is chosen so that the pulse from the output of the element 53 delays the flip-flop 25 to one state only after it is on the counters. 17-19, registers 20 and 21, count 22, the process of forming the codes is complete. The binary code of the required number of processors obtained on the counter 17 is fed to the first input of the first comparison circuit 23 by more c to the first input of the third circuit 23, compare more. The binary code is doubled. the required number of processors obtained at the counter 22, is fed to the first input of the second circuit 23, comparing with more. The binary code of the number of free processors obtained on the counter 18 is fed to the second inputs of the second and third circuits 23-, the comparison is more. The binary code of the sum of the number of free processors and the number of processors occupied by duplication, obtained at counter 19, is fed to the second input of the first circuit 23. compare more. Thus, the first comparison circuit 23 by more implements the inequality of the second comparison circuit 23g by more — the inequality,, (d) and the third by the inequality (5) If the number of processors required to complete the task (ny) 5 is greater than the sum of the number of free processors and processors occupied by duplication (), t. If inequality (1) is satisfied, then a single signal is generated at the output of the first comparison circuit 23 by more. This signal is fed to the first input element And 32, on the second; the input of which receives a single signal from the trigger 25. As a result, a single potential appears at the output of AND 32, which enters the fault bus 10 as a refusal signal. In addition, this. the signal through the OR element 44 clears the counters 17-19, and 22, the registers 20 and 21, and the trigger 25 switches to the zero state. However, when inequality (1) is fulfilled, a zero signal is generated at the output of AND 33, which is. blocks the outputs of the second and third comparison circuits by more. If inequality (1) is not fulfilled, then at the output of the element And 33 a single potential appears, which allows the signal from the output of the second comparison circuit 23 to pass through the elements AND FOR and 35 more. Then, if the double number of processors (2) required for execution is greater than or at least equal to the number of free processors (n), t. e. Since inequality C2) is not fulfilled, then at the output of the second comparison circuit 23 by no more than a single signal appears. Therefore, the zero signal from the output of the AND 34 element blocks the output of the third comparison circuit 23j, and at the output of the AND 35 s element, the appearance of a single potential from the trigger. 25, a single signal is generated, which, through the OR 44 element, zeroes counters 17-19. and 22, registers 20 and 2, and toggles trigger 25 to zero. In addition, this signal is fed to the input, which controls reception in register 12 with an offset, and through an input element SHSh 15 to an input that controls reception in shift register 4, ensuring reception of the code of the required number of processors in registers 12 and 4 of shift. In the case of coincidence of units in the bits of register 4 shift and register 2 readiness. the corresponding groups of elements AND 5 Pa: permit the passage of the code of the task number, which enters the task number buses 9, to the input of the corresponding processors for execution. When a task code appears at the outputs of groups of elements 5, signals appear at the outputs of the corresponding groups of elements 6, which embrace the corresponding triggers of the shift register 4 and register 2 of readiness. At the same time, in the event of a coincidence of units in the bits of the shift register 12 and the readiness register 2, the corresponding groups of elements 5 permit the passage of the task number to the input of the corresponding processors for duplicate execution. When a code of the job number appears at the outputs of groups of IZ elements, signals appear at the outputs of the corresponding elements OR 6, which embrace the corresponding triggers of the shift register 12, the ready register 2 and the corresponding triggers of the duplication register 13 are switched to one. By this time, the signal from the output of the element 35, the passage through the element 48, 48 sets in one state the trigger 27, If the number of triggers of registers 4 and 1 of the shift remaining in the state one is different from zero, then at the output of the element iljfll 3 at the end of the distribution, a single signal is formed, which, through the second element HE 49j, passes to the zero input three hera 27, not changing its state. The potential from the unit output trig 27 permits the passage of pulses generated by the generator of 59 pulses through the corresponding element and memory to the inputs that control the shift of registers 4 and 12 of the shift where the code of the required number of processors shifts: in register 4 of the shift in the direction of increasing processor numbers, and in register 12, shifting the descending direction of these numbers. - When units coincide in the corresponding bits of registers 4 and 12 shift and ready register 2, a task number code is transmitted through a group of elements And 5 to the inputs of the corresponding processors for execution and duplication, resetting the corresponding triggers of shift registers 4 and 12, register 2 readiness and switching into one state the corresponding triggers of the duplication register 13. If all of the shift registers 4 and 12 are zeroed, then the output of the OR element 3 of the distribution end is a zero potential which through the second element NOT 49 enters the zero input of the trigger 27, switching it to the zero state. At the single output of the trigger, a zero signal is generated, which prohibits the passage of pulses from the generator output 59 pulses through the AND 39 element. If there are twice the number of processors needed to complete a task (2 n), less than the number of free processors (p. ), t. e. Inequality (2) is satisfied, then a single signal is generated at the output of the second comparison circuit 23 by more. This signal is fed to the second input element And 34, the first input of which receives a single potential from the output of the element And 33, and the third input - a single signal from the trigger 23. As a result, at the output of the element And 34, a unit potential appears, which permits the passage of the signal from the output of the third comparison circuit 23j by more elements And 36 and 37. Then, if the number of free processors (p) is greater than or at least equal to the number of processors needed to complete the task (n,), t. e. Since inequality (3) does not hold, then at the output of the third circuit 23, a comparison of a single signal does not appear. Consequently, the output element And 36 will be a zero signal, and the output element And 37 with the arrival of a single potential with a trigger. 25, a single signal appears, which, through OR 45 and 44 elements, zeroes counters 17-19 and 22, registers 20 and 2I, and triggers 23 to the zero state. In addition, this signal through the elements OR 45 and 15 is fed to the input controlling the reception in the shift register 4, ensuring the reception of the code of the required number of processors in this register. In case of coincidence of units in the bits of the shift register 4 and the readiness register 2, the corresponding groups of elements 5 allow the job number code passing on the job number pins 9 to the inputs of the corresponding execution processors. When the code of the job number appears at the outputs of groups of elements 5, signals appear at the outputs of the corresponding groups of elements 6, which embrace the corresponding triggers of the shift register 4 and the ready register 2. By this time, the signal from the output of the element And 37, the passage through the element OR 48, sets in one state the trigger 27. If the number of triggers of the shift register 4 remaining in the single state is different from zero, a single signal is generated at the output of the OR element 3 of the distribution end, which through the second element HE 49j passes to the zero input of the trigger 27, does not change its state. The potential from the single output of the trigger 27 permits the passage of pulses generated by the generator 59 of pulses to the input that controls the shift, the shift register 4, where the code of the required number of processors shifts in the direction of increasing the processor numbers. When the units in the corresponding bits of the shift register 4 and the readiness register 2 coincide, the task number code is output through the group of elements And 5 to the inputs of the corresponding processors and the corresponding bits of the shift register 4 and readiness register 2 are reset, all of the shift register trigger 4 are zeroed, then The output of the element 3 of the end of the distribution appears zero potential, which, after the second element NOT 49j, enters the zero input of the trigger 27, switching it to the zero state. At the single output of the trigger, a zero signal is generated, which prohibits the passage of pulses from the generator output 59 pulses through the element I 39. If the number of processors required to complete a task (PU) is greater than the number of free processors (pr), t. e. SZ inequality is satisfied), then at the output of the third circuit 23, a single signal is formed on a larger one. At, the signal arrives at the second input of the element I 36, the first input of which receives a single potential from the output of the element And 34, and the third input receives a single signal from the trigger 25. As a result, the output element And 36 appears. single potential,. The OR 45 and 15 elements go to the input that controls reception in the shift register 4, providing the reception of the code of the required number of processors in this register, and counters 17-19 and 22, registers 20 and 21, using the elements SHSh 45 and 44, and triggers trigger 25 to zero. In addition, this potential starts the second generator 582. single-pulse: At the same time, the single-position code of the number of free processors, located in register 21, goes to the first inputs of single-bit equality comparison circuits 24, to the second outputs, which receive the corresponding bits of the single-position code of the number of processors needed to complete the task, which is in register 20. If identical signals (both zeros or both ones) are applied to the inputs of a one-bit comparison circuit, then a potential appears at the output of the circuit; if there are different signals at the input, then a single potential is formed at the output. Thus, at the outputs of the group of single-bit comparison circuits 24 for equality, a single-position code is formed, which is a set of units J the number of which is equal to the difference between the number of processors needed to perform the task and the number of free processors (PC-Pr) O Impulse c. the output of the second generator 58, delayed in the group of elements 55 of the delay, allows the sequential passage of the units of the difference code (PU, -Pc) through the group of elements AND 38. Each unit from the output of the corresponding group of elements AND 38 enters through the elements OR 46 and 47 at the input, which controls the 5 shift register of the removal register 11, shifts the register contents to the right, which releases the higher bit to receive the next difference code unit () through the element 57 delays. The signal from the output of the last delay element 55 of the group is delayed by the delay element 56 (the delay time is chosen so that the pulse from the output of the delay element 56 switches the trigger 26 and 28 to one state only after the code generation process is completed on the register 11 of the code). i In the case of coincidence of units in the bits of register 11 of removal and register 13 of duplication, with occurrence of a unit potential from trigger 26, the corresponding groups of elements And 5 permit the passage of the code of the task number, which arrives after the task number, to the input of the corresponding processors for their release from duplication. When the code of the task number appears at the outputs of groups of elements 5, signals appear at the inputs of the corresponding groups of elements 6, which encircle the corresponding triggers of the duplication register 13 and the register of removal, and switch the corresponding triggers of the readiness register 2 into one state. 179 If the number of flip-flop register triggers remaining in the single state is different from zero, then a single signal is generated at the output of the LL 16 terminating element, which passes through the first inverter to the zero input of the flip-flop 27, its status does not change. The potential from the single output of the trigger 26 permits the passage of pulses generated by the pulse generator 59 through the corresponding element AND 39 and element SHSh 47 to the input that controls the shift of the removal register 11, where the difference code (n, 1) is shifted in the direction of decreasing processor numbers . The ilpH coincidence of units in the corresponding digits of the register 11 of the removal and register 13 of the duplication occurs when the code of the number is transmitted through the group of elements AND 5 to the inputs of the corresponding processors in order to exempt them from duplicate execution of tasks, zeroing the corresponding triggers of the register I1 of the removal and register 13 of the duplication and switching to the unit state of the corresponding triggers of the readiness register 2. If all the triggers of register 1 I are reset, then the output potential of the L-16 element of the removal stage is zero potential, which through the first element NOT 49 enters the zero input of the trigger 26, switching it to the zero state. At the single output of the trigger, a zero signal is generated, which prohibits the passage of pulses from the output of the generator 59 pulses through the corresponding element AND 39. At the same time, a single signal from the output of the first element HE 49j passes through the element 40, to the second input of which a single potential is output from the trigger 28, and the MS 48 element sets the trigger 27 to one state. If the bits of the shift register 4 and the read register coincide, 2 groups of elements AND 3 allow the input task number code to pass. s relevant processes. When a task number code appears at the outputs. groups of elements 5 and 5, a signal appears at the outputs of elements 111 6 that null the triggers of the shift register 4 and the readiness register. If the number of triggers of the shift register 4 remaining in one state, different from zero, the output of the OR element 3 of the distribution end generates a single signal that passes through the second element HE 492 to the zero input of the trigger 27, does not change its state. The potential from the single output of the trigger 27 permits the passage of pulses generated by the pulse generator 59 to the input that controls the shift of the shift register 4, where the code of the required number of processors is shifted in the direction of increasing processor numbers. If the bits of register 4 shift and register 2 of readiness coincide, the code of the task number through the group of elements And 5 at the inputs of processors and reset of the bits of register 4 of shift and register 2 of readiness occurs. If all the triggers of the shift register 4 are set to zero, then at the output of the WL 3 element of the distribution end a zero potential appears, which through the second element NOT 49j enters the zero input of the trigger 27, switching it to the zero state. At the single output of the trigger, a signal is generated that prohibits the passage of pulses from the output of the generator 59 pulses through the element 39. Thus, the proposed device allows to increase the reliability of tasks due to the use of natural redundancy for duplicated task execution. Suppose task Z is in the multiprocessor computer system containing four identical processors, which reduces to task execution to perform any task Zj,. . and the whole set of tasks, Z- (J Z is performed during the time T T II tt; (Ti? -k t Vt, k where Ti is the 1st time interval. 19 Between tasks 2 there are informational and control communications that are specified by the adjacency matrix. Suppose that for execution of tasks, Z and Z, time t is required, and for execution of tasks Z, Z and Z, time 2J. With existing links between tasks. and Zj € Z, the known device, allocates the IR for execution as follows: setting Z to the first processor on the interval T; setting Zj, to the second processor in the interval T; 1; assigning Zj to the first processor on interval T, assigning 1c to second processor on interval Tj + tj setting Zj to third processor on interval Then, assuming that the time interval T is much longer than the distribution of task ZJ, get that the accuracy of the tasks P (Z) characterized by the likelihood of correct implementation, is equal to r,. , where P (Zj) is the probability of correct execution of the j-ro task. Since Tr and all processors are identical, and failures in different processors are independent of each other, then) Po. when assigning tasks to a known device, the probability of correctly executing tasks Zj is equal to Р „(2) Ро; Ne (25); RI (ZS) PO Pu (2g,) Po; P, (Z,) Pa; And the reliability of the task execution Z is P ,, (Z) nP (Zi) P. When assigning tasks Zj to the proposed device, they are performed as follows: task Z is completed on the first Processor and simultaneously on interval t on the second processor, task Zj is performed on the third processor and simultaneously on interval i on the fourth processor; setting Z is performed on the first processor and simultaneously on the second processor on the interval); task Z. on the third processor on the interval (Zj, + Zi); task zj. - on the fourth processor in the interval () It is assumed that the results are output through an advanced device which, in the sense of reliability, is ideal. In this case, the probability of the correct implementation of the coding task P (Zj) is equal to PytV P. j (Iir-1- (i-Po). P ,, cz: 5) 1- (1-p „Д Ру (1ц) Р. (g. 51 PO Reliability P (Z) is determined by the following relation PCZ). np (lj) pJ {2-p S2-P /). Then, in authenticity,) -Pn p ,,. RP) P (g-rn "(a-p„ b-1 - 1 ooo7o Pola P (, U, 93, we get W (2-0.93f (2-0.93) -). 100% 30%, while with PO 0.9 (2-0.9) (2-0.9) -. . As the above calculations show, the developed device allows to increase the reliability of the tasks by using natural redundancy. Claim 1, A device for assigning tasks, containing a control unit, a shift register, the first element OR, the first group of elements OR, the register of readiness, the first group of elements Hj, the first inputs of the elements AND of the first group are connected to the corresponding and outputs of the register of readiness, the inputs of which are connected to the readiness inputs of the main processors of the device, the outputs of the readiness register are connected to the code inputs of the free processors of the control unit whose failure output is connected to the output of the device failure, moves the code number of a necessary process. The port of which is connected to the information inputs of the shift register and to the code inputs of the number of necessary processors of the control unit, the outputs of the shift register to the second inputs of the AND elements of the first group and the first group of inputs of the first OR element whose output is connected to the input of the distribution end of the control unit, the control output the shift of which is connected to the shift control input of the shift register, the reset inputs of which are connected to the first reset inputs of the ready register. to it and to the outputs of the elements OR of the first group, whose inputs are connected to the outputs of the corresponding AND elements of the first group and to the outputs of the main task number of the device, the third inputs of the AND elements of the first group are connected to the inputs of the device number of the device number, characterized in that functionality due to the use of natural redundancy for duplicating the fulfillment of the task, the duplication register, the second group of OR elements, the third group of OR elements, the register of removal, the second the element OR, the third element OR, the fourth element of the CMM, the additional shift register, the second group of elements And the third group of elements AND whose outputs are connected to the corresponding inputs of the elements OR the third group and to the corresponding outputs of the number of the device task being removed, are connected with the information input of the duplication register, the outputs of which are connected to the first inputs of the AND elements of the third group and with the code inputs of the processors occupied by the duplication of the control unit The shift control register of the pickup register of which is connected to the shift control input of the register of the pickup, the outputs of which are connected to the second inputs of elements AND of the third group and the inputs of the fourth OR element, the output of which is connected to the input of the removal end of the control unit, the outputs of the completion of the removal code formation which are connected to the third the inputs of elements AND of the third group, the fourth inputs of which are connected to the inputs of the device setting number, the inputs of the second element OR, and to the first inputs of the elements AND of the second group, which are which are connected to readiness register outputs, and the third outputs - with the second inputs of the second group of inputs of the first element OR and with the inputs of the additional shift register, the information inputs of which are connected to the code inputs of the number of necessary processors of the device, the outputs of elements AND of the second group are connected to the output numbers of the duplicated device task and the inputs of the second group of elements OR, whose outputs are connected to the second reset inputs of the readiness register, to the redundancy register setting inputs and to the reset inputs th shift register, the control input. the reception of which is connected to the control output of receiving the additional shift register of the control unit and the first input of the third element OR whose second input is connected to the control output of the reception of the shift register, the output of the third element OR is connected to the control input of receiving the shift register the shift of the control unit, the input of the reference number of which is connected to the output of the second element OR, and the output of the serial input - to the input of On the input of the register of removal, the reset inputs of which are connected to the inputs of zeroing of the register of duplication, the inputs of the installation of the register of readiness and the outputs of the third group of elements OR.

2. The device according to claim 1, characterized in that the control unit contains two generators of single pulses, four triggers, the first, second, third and fourth group of elements AND, the first, second, third and fourth group of delay elements, the first and second registers, the first, second, third and fourth counters, three comparison schemes by more, a group of comparison elements for equality, two elements NOT, seven elements OR, nine elements AND, four delay elements, a pulse generator, the output of which is connected to the second input of the seventh element Nickname to the first input of the eighth element I, the output of which is connected to the output of the shift control of the block and with the zero input of the third trigger, the direct output of which is connected to the second input of the ninth element And, the first input of which is connected to the output of the first element the house of the second trigger, the direct output of which is connected to the output of the end of the formation of the code for the removal of the bhyuk and to the first input of the seventh element I, the output of which is connected to the second input of the seventh element i-LTH whose first input is connected to the input of the second element nta delay and, to the output of the fifth element OR, the inputs of which are connected to the outputs of the even-vertex group of elements AND, the first input of the first element AND of the fourth group is connected to the output of the second generator of single pulses and the input of the first delay element of the fourth group, the output of qq element delays of the fourth group (, 2, ..., t-1), where -t is the number. processors in the processor unit) is connected to the first input q + 1 element of the fourth group and the qs-1 input of the element and the delay of the same group, the output (tl) ro of the delay element of the fourth group is connected to the input of the first delay element, output which is connected to the single input of the third trigger and to the single input of the second trigger, the second inputs of the fourth group of elements I are connected to the outputs of the group of comparison elements for equality, the first inputs of which are connected to the outputs of the second register, and the second platoons to the outputs of the first register Tra, informational inputs of which are connected to the code inputs of the number of required -processors of the control unit and to the second inputs of the first group of elements I, the first input of the first element. And the first group is connected to the output of the first generator of single pulses, to the input of the first delay element of the first group, to the input of the first delay element of the second group and to the first first element and the second group, the output of each i-ro delay element of the first group ( I 1,2, ..., t), except for%, is connected to the first .in the remote control of the first group and to the input (iH-l) -ro of the delay element of the same group, output of the first delay element t-ro the group is connected to the control input of the fourth counter, the outputs of the first group of elements AND are connected to the inputs of the first element ORT, the output of which is connected to the installation input of the fourth counter, the outputs of which are connected to the first inputs of the second cxetoii comparison by more, the second inputs of which are connected to the second inputs of the third comparison circuit to more and the outputs of the second counter, the installation input of which is connected to the output of the second CM element , the input of the third delay element, the unit input of the second register and the second input of the third element OR, whose inputs are connected to the outputs of the second group of elements AND, the first inputs of this group are connected to the inputs the code of the number of free processors of a block, the output of each j-ro delay element (, 2, ..., tl) is connected to the input (j + l) -ro delay element of the same group and to the second input (j + l) -ro element And the second group, the output (tl) -ro of the delay element of the second group is connected to the first input of the first element AND of the third group and to the input of the first delay element of the third group, the output of the K-th delay element of the third group (, 2, ..., - t / 2-l) is connected to the first input of each (K + 1) -th element AND of the third group, the second inputs of the third group of elements AND are connected to the inputs of the code number processors, duplicated, and outputs to the first input of the third OR element, the output of which is connected to the installation input of the third counter, the output (t / 2-1) -ro of the delay element of the third group is connected to the input of the fourth delay element, the output of which is connected to a single input of the first trigger, the direct output of which is connected to the second inputs of the first and second elements AND and to the third inputs of the third, fourth, fifth and sixth elements AND, the output of the fourth element OR P. DSC.17K. -itiH to the reset input of the first, the second ;, the third and fourth counts. and the first, second and third register. and to the zero input of the first trigger, the first input of the fourth SHY is connected to the failure output of the control unit and to the output of the first element And, the first input of which is connected to the output of the first comparison circuit and more to the first input of the second element And, the output of which is connected to the first input of the third the AND element and the first input of the fourth AND element, the output of which is connected to the second input of the eighth OR element, the output controlling the reception of the additional shift register of the block and the second input of the fourth STI element, the third input of which Connected to the control output of the reception of the shift register of the block and with the output of the sixth element OR, the first input of which is connected to the output of the fifth element AND and the input of the second generator of single pulses the second input of the sixth element SHS is connected to the first input of the eighth element SHS and with the output of the sixth element And, the first input of which is connected to the output of the third element And the first input of the fifth element And and the first input of the sixth element And, the second input of which is connected to the second input of the fifth element Ne the output of the third comparison circuit for pain above, the first input of which is connected to the output of the first counter and to the first input of the first comparison circuit by more, the first input of which is connected to the output of the third counter, 26 the output of the second comparison circuit is more connected to the second input of the third element And the second input of the fourth element And, the output of the second delay element is connected to the output of the sequential input of the block, the input of the first element is NOT connected to the input of the end of the block removal, the input of the second element is NOT connected to the input of the end of the block distribution, and the output is to The fourth input of the fourth trigger, a single input of which is connected to the output of the eighth element OR, the third input of which is connected to the output of the ninth element AND, the direct output of the fourth trigger is connected to the second input of the eighth element And, the output of the seventh element OR is connected to the control output of the block shift, the input of the first generator of single pulses is connected to the input of the block reference number. Sources of information taken into account during the examination 1. USSR author's certificate No. 468240, cl. G 06 F 9/00, 1973. 2. USSR author's certificate No. 629538, cl. G 06 F 9/00, 1978 (prototype).

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