SU902021A1 - Device for finding optical solution of one-dimensional cutting out problem - Google Patents

Description

The invention relates to computer technology and can be used to automate the cutting of semiconductor single crystals into billets of two grades, as well as to optimally solve the problem of one-dimensional cutting of other materials, if the search algorithm for the optimal solution belongs to the class of algorithms that can be implemented using the device.

A device for cutting is known, which contains comparing units, setting scales, a clock generator, AND elements, an input unit, a counter, a coefficient root selection unit, an output unit, a multiplication unit fl].

However, this device uses a large number of searchable options, which reduces its effectiveness.

Closest to the proposed one is a device that contains an input unit, a comparison unit, a logical signal generation unit, scale resistors, an I element, switching units, operational amplifiers, a register and a control pulse shaper, the first input of which is connected to the device input, five outputs of the input unit through series-connected the first switching unit, the first group of scale resistors and the first operational amplifier are connected to the first input of the comparison unit. The first, second, third and fourth outputs of the input unit through the second switching unit connected in series, the second group of scale resistors and the second operational amplifier are connected to the second input of the comparison unit, the output of which is connected to the first input of the And element, the inputs of the logical signal-forming unit are connected to the outputs of the register and with the third output of the control pulse shaper, the first output of the signal conditioning logic unit is connected to the output of the device, the second output is connected to the control input p Giustra and a second input of the control pulses, and control outputs connected respectively to the control inputs of the switching units _s £ 2j.

A disadvantage of the known device is the relative complexity of its circuit, more precisely, of its control part, which includes ten AND elements and a counter, and both the counter outputs and the memory register outputs are inputs of a signal generating logic block, which with such a large number of inputs turns out to be very bulky.

The purpose of the invention is to simplify the device.

This goal is achieved by ₂ o that the device containing the parameter input unit, the comparison unit, the switching units, the encoder, analog adders, the element And and the clock pulse generator, the first input of which 25 is connected to the control input of the device, five outputs of the parameter input unit through in series connected the first switching unit and the first analog adder connected to the _m first input of the comparator, the first, second, third and fourth outputs of the input unit parameters via a serially coupled second unit The switching circuit and the second analog adder are connected to the second input of the comparison unit, the output of which is connected to the first input of the And element, the second input of which is connected to the first output of the clock generator, the second output of which is connected to the control input of the encoder, the first output of which is the output of the device, the second output is connected to the second input of the clock generator, the third and fourth outputs of the encoder ^{45 are} connected to the control inputs of the first and second switching units, respectively, contains a register shift, the outputs of which are connected respectively to the inputs ⁵⁰ shifra- torus shift input - is connected to the third output of the clock pulse generator, first and second inputs of the shift register are respectively connected to the output of AND ⁵⁵ and the second swing You are a coder.

In FIG. 1 shows a block diagram of a device; in FIG. 2 is a search algorithm implemented by a device, 'in FIG. 3 “object to be cut. The device circuit includes an input unit 1 of parameters, blocks 2 and 3 of switching, a group of scale resistors 4,5, ..., 6, a group of scale resistors 7 and 8, ..., 9, operational amplifiers 10 and 11. At the operating rooms amplifiers and large-scale resistors made analog adders, block 12 comparison, element And 13, the clock generator 14, the register 15 shift, the encoder 16 and the input 17 of the device.

The input unit G allows you to set at its first four outputs constant stable negative voltages proportional to the initial data of the solved cutting problem. These voltages can be set manually - by the operator, or automatically - by signals from a device that measures the corresponding values.

Operational amplifiers 10 and 11 are made summing. The output signal of the comparison unit 12 has two levels, namely, zero and one. A single signal is present at its output only when the voltage supplied to the first input of block 12 from the output of the first operational amplifier 10 is strictly less than the voltage supplied to its second input from the output of the second operational amplifier 11.

The clock generator 14 has three pulse outputs and two Start and Stop inputs. In the initial state, there are no pulses at the outputs of the generator t4. After applying a pulse to the input, the bottom starts generating at the output connected to the shift input of the 15 ”register a sequence of pulses with period T. These same pulses, delayed by the time T / 2 and 2T / 3, appear on its other outputs, respectively. The pulse supplied to the second input (input ^ Stop) of the generator 14 from the output of the encoder 16, returns it to its original state.

The register 15 is made shift, the number of its bits is one more than the maximum number of algorithm conditions that need to be checked to find the optimal solution. Register content shift

902021 6 by applying pulses (to the input of the shift. The pulse received at the input of register 15 from the second output of the encoder 16 sets it to its initial state, in which the first bit contains one 5 and all the others contain zeros. A single input of the first bit of the register is connected with the output of the element And 13.

In other words, the initial state is LLC ... 01, the shift is carried out to the left * i.e. after each shift, the first discharge is in the zero state, and after K shifts, the K + 1st discharge will be in the single state, and all discharges to the left of it will be in the zero state.

The inputs of the encoder 16 connected to the outputs of the register 15 are potential, and the input connected to the output of the generator 14 is pulse. 20

The signals at the outputs of the encoder 16 are generated when a pulse arrives from the output of the generator 14. The coding of decisions, as well as the control signals of switching units 2 and 3, 25 providing the required connections, can be chosen by anyone, depending on the elements used and other circumstances.

The output of the device can be 30 keys to the indicator of the optimal solution, if the decisions are made by the operator, or directly to the control inputs of the executive devices of the automatic system of optimal 35 cutting.

In the rectangles of the flowchart of the algorithm (Fig. 2), the conditions being checked are written, and in the circles are the symbols of the decisions made. A + sign means fulfilling, and a sign is not fulfilling the corresponding condition. Decisions made are indicated as follows: ₄₅

N0 ~ do not produce cuts; implement the entire single crystal (ingot) as a blank of the zero grade (reject);

N1 - do not produce cuts, sell the entire ingot as a first-grade billet;

N2 - do not produce cuts, sell the entire ingot as a second-grade billet;

Av22, Av20, AvOO - make cuts at the quince points, the first and second digits indicate the grade of the workpiece, obtained respectively from the left and right parts of the ingot (its middle part will always be the first grade);

a2, a0 - cut at point a, the number indicates the grade of the workpiece obtained from the left side of the ingot (the right part will always be the first grade)) h - cut at the point h, the left side is the second grade , right - of the first, 'ah - to make cuts at points a and Lh, both cut ends of the ingot are preforms of the second grade, and the middle is a preform of the first grade;

hb - to make cuts at points h and b, the left side, while the workpiece is of the second grade, the right is zero, the middle is the first;

hh - to make cuts at points h and L = h, the middle of the ingot is at the same time the first grade and the other two parts are the second.

It is assumed that the ingots sorien ⁴ · ted so that it is easy to provide, for example, in step measurement value a, b, L before cutting ingots. ~~

In the initial state, the generator 14 is in the Stop state, i.e. there are no pulses at its outputs. The first bit of register 15 is set to a single state, the remaining bits to zero. At the corresponding outputs of input unit 1, voltages are established proportional to the values characterizing the object to be cut.

The principle of operation of the device consists in the automatic calculation using the operational amplifiers 10 and 11 of the left and right sides of the inequalities appearing in the algorithm shown in FIG. 2, and in verifying their implementation, according to the algorithm, until an optimal solution is found. In this case, the next condition to be checked is automatically selected depending on the results of previous checks in accordance with the algorithm. With the indicated initial state of the register 15, all outputs of the switching unit 2 and 3 are grounded. .

The device is started by applying a pulse to the input 17 of the device. The pulse from the output of the generator 14 shifts the contents of the register 15 by

Ί 90 one bit (i.e., the register goes into the state 00 ... 010, freeing the first bit to receive the result of checking the first condition of the algorithm). With the new state of the register, i.e. with a new code combination at the inputs of the encoder 16, the switching unit 2 connects the input of the operational amplifier 10. through a resistor to the third output of the input unit 1, and the switching unit 3 connects the input of the operational amplifier 1 1 through a resistor to the fourth output of the input unit 1.

If it turns out that L <h (the first inequality of the algorithm), a single signal appears at the output of the comparison unit 12, i.e. the element And 1J opens, and the output pulse of the generator 14 passes through it, setting the first bit of the register 15 in a single state, i.e. fixing in it a positive result of checking the first condition. If the condition is not met, the first bit of register 15 remains in the zero state.

, If the first condition is met, then with the arrival of a pulse from the output of the generator 14, the corresponding code combination is generated at the output of the device, and at the output of the encoder 16 connected to the second input (Stop input) of the generator 14, a pulse is generated that returns the generator 14, as well as the register 15 to the initial state, and the execution of the algorithm ends there.

If the first condition is not met, then the pulses do not appear at the output of the device, the generator continues to work, and the second pulse from its output again shifts the contents of register 15, which takes the form 00 ... 0100. 'With this input code combination, the encoder 16 provides the connection of the inputs and outputs of blocks 2 and 3 of the switching necessary to check the next inequality of the algorithm.

If it is satisfied, then, similarly to the previous one, the output pulse of the generator 14 puts the unit in the first bit of the register 15, and the pulse from the other output of the generator 14 generates an optimal solution code N2 in the output of the device, as well as a pulse at the output of the encoder 16, which returns the generator 14 and register 15 in the initial state. EU

8, whether the second condition is not satisfied, the operation of the device continues in exactly the same way, providing verification of conditions according to the algorithm shown in FIG. 2 until finding the optimal solution.

The fixed voltage at the fifth output of input block 1 is selected equal to unity (on an appropriate scale), so that connecting a resistor to this output provides the required voltage at the output of the operational amplifier. Operational amplifier 10 calculates the left sides of the inequalities, and operational amplifier 11 calculates the right ones.

As can be seen from FIG. 2, the search may require verification of a maximum of ten conditions, which is why the number of bits in the register 15 in this case (i.e., when implementing this particular algorithm) is 11. Moreover, in the discharge, the number of which is one more than the number of the condition being checked, always contains one Thus, the position of the first _l unit (from left to right) in the code combination contained in the register uniquely determines the number of the condition being checked. The implementation of resistors 4 to 9 adjustable makes it easy and simple to rebuild the device when changing the values of Co, C ^, C ^, Cp.

Claims (2)

1. USSR author's certificate (G kS76Q6, class G 06 J 1/00, 6 About F15 / 20, 1971. 2.A8T (certificate of the USSR on the application ff 2503987/2 1, ky G About F 15/20, 1977 (prototype).