SU875383A1 - Device for majority retrieval of signal - Google Patents

Description

(54) MAJOR ELECTION DEVICE

SIGNAL

The invention relates to computing and can be used as a device for the majority of the signal when it is replicated three times, for example, in processors with triple-counting. A device for the majority signal sampling at its threefold repetition is known, containing shift registers, control gates, comparison circuits based on sequential recording of information in shift registers, comparing the incoming and previously recorded information codes and sampling a reliable code according to the principle. Two out of three There is a greater complexity, due to the presence of switching elements, a triple number of shift registers and the complexity of logic. The closest technical solution to the present invention is a signal sampling device containing a data bus, a reset bus, a clock bus, a switch element, a bit comparison element, a control valve and a ternary shift register, the output of which is connected to the first inputs of the bit comparison and controlled valve whose second inputs are connected to the information bus and to the first input of the switching element, the second, third inputs and output of which are connected respectively to Exit circuit bit-wise comparison, a controlled valve and to the inlet of ternary shift register whose setting input is connected to the reset bus 2. A disadvantage of the known device is a large hardware and functional complexity. The hardware complexity of the device is due to the presence of a switching element, a ternary shift register, and bitwise comparison circuitry. The functional complexity is due to the relatively large number of operations for selecting a reliable code, including switching operations, shifting, bitwise comparison. The purpose of the invention is to simplify the device for the majority signal sampling, which makes it possible to significantly reduce the instrumental and functional complexity of the device and increase its reliability.

The goal is achieved by the fact that in a majority signal sampling device containing an information bus, a reset bus, a clock bus, a two-bit shift register and a controllable valve, the first input of which is connected to the information bus, the reset bus is connected. An input of a two-bit shift register, an information input and a clock input of a two-bit shift register are connected respectively to the information bus and to the output of a controllable valve, the second input of which is connected to the clock bus.

The drawing shows a block diagram of the proposed device for the primary sampling of the signal.

The device contains a two-bit shift register 1, a controllable valve 2; clock bus 3; information bus 4, tire 5 reset and output bus 6.

The information bus 4 is connected to the first input of the controlled valve 2 and to the information input {D of the two-bit shift register 1, the clock input (s) and the installation input (.9) of which are connected respectively to the output of the controlled valve 2 and the reset bus 5, the output of the second bit of the two-bit shift register 1 is connected to the output bus 6.

The device works as follows.

Before the signal begins to be sampled (or after it), the reset signal is reset on the reset device bus 5, the two-bit shift register 1 is reset. On the information bus 4 of the device three times 1; 1 a signal equal to 1 can occur. any repetition. When signal 1 arrives at the corresponding input of the controlled valve 2, the enabling signal and information arriving at the information input (1) of the two-bit shift register 1 will be recorded according to the shift signal synchronously with the information signals on the clock bus 3 of the device register 1. When signal 1 is re-received, a unit is shifted, which arrived in the first repetition in the second register register 1. After the third signal was received, the first one is pushed out of register 1, its location is maet unit supplied are at the second repetition. Thus, a signal is generated at the second information output of the two-bit shift register 1. equal to 1, coming to the output device. The first information output of the two-bit shift register 1 is not activated and is not

is used. In case of an error in one of the repetitions (O 1 1 1 O 1, 1 1 O combinations), when a zero information signal is received at the corresponding input of the controlled valve 2, a level is created that prohibits the shift of the shift signal from the clock bus 3 to the CC- input) shift register 1. The register maintains its status. When the two remaining units arrive at the second bit of information in register 1, in the case of a three-fold signal O, no shift occurs in register 1, and the second bit retains its zero value. In the event of an error in one of the repetitions (1 O O, O 1 O, O O 1 combination), when an erroneous unit is received, it will be entered only in the first digit of the shift register 1, and in the second information bit, the output will be signal equal to O. Thus, a majority of the signal is sampled on the principle of two out of three. The device performs the majority selection of a one-bit word when it is repeated three times.

To make a majority choice of the h-bit word, it is necessary to use m-data devices in which the reset inputs of the two-bit shift registers are combined

.and the second inputs of the control valves are combined.

The proposed device in terms of equipment composition and functionality / complexity is much simpler known. In the known device, a ternary shift register is used, in the proposed one, a single two-bit shift register. In addition, in the proposed device there is no switching element, a bitwise comparison circuit and, as a result, a switching operation and a comparison operation.

Claims (2)

1. US Patent 3781792, cl. Q 06P 11/00, 1973. 2. Authors certificate of the USSR 328459, cl. Q 06P 11/00, 1972.