SU834874A2 - Time interval shaper - Google Patents

Description

(54) TEMPORARY INTERVAL FORMER

one

The invention relates to a pulse technique, can be used in electronic devices to memorize the time interval.

According to the main author. St. No. 496660 is known a shaper of a time interval, which contains an annular circuit of n serially connected delay cells, two triggers and a logical element I, the inputs of the 1st and Kth delay cells being connected to the sources of information signals, the input, one or several delay cells and Trigger installation inputs O are connected to the reference source, counting trigger inputs are connected to outputs 1 and K of the delay cell, and trigger outputs are connected to AND 1.

A disadvantage of the known device is the eifo low speed (there is little relation between the maximum duration of the time interval and the generation period).

The purpose of the invention is to increase the speed of the device.

The goal is achieved by the fact that in the time interval former, which contains an annular circuit n a successor

but the connected delay cells, two triggers and a logical element, And, the inputs of the 1st and K-th delay cells are connected to the sources of information signals, the input of one or more delay cells and the inputs of the setting O triggers are connected to the source of the reference signal, the counting inputs of the triggers connected to the outputs of the 1st and K-th delay cells, and the outputs of the flip-flops are connected to the element And, two additional triggers with a counting input are introduced,

0 elements 2 AND-OR, ZI-OR and the switch, the inputs of which are connected to the outputs of the delay cells and the buses of the input and reference signals, the control outputs to the inputs of the 1st and K-th delay cells, and logical outputs to the inputs of the element

5 ZI-OR, the input of the first element AND of which is connected to the output of the element 2И-OR the input of the second element AND with the output of the main element AND, the input of the third element AND with the output of the first main trig. Hera and with the counting input of the first additional trigger, the outputs of which are connected to the inputs of the element 2И-OR, the other inputs of which are connected to the outputs of the second additional trigger, counting

the input of which is connected to the output of the second main trigger, and the input of the installation O is connected to the input of the installation O of the first additional trigger and to the reference signal bus.

The switchboard contains three channels, each of which consists of a series-connected OR element, a first AND element, an RS-flip-flop and a second AND element, and the R-inputs of the triggers are connected and connected to the reference bus, the inverse trigger output of a single channel is connected to the inputs of the first elements And the other two channels, the direct outputs of the triggers are the logical outputs of the switch, with the outputs of the second And elements of the two channels being OR connected, and all the And elements are interconnected via a single input.

FIG. I presents the functional diagram of the proposed shaper; in fig. 2 and 3 are timing diagrams that explain the principle of its operation.

The shaper of the time interval consists of an annular circuit 1 of serially connected delay delay cells, 1-2 ... 1-P main triggers 2 and 3, the main element 4 AND, switch 5, which contains elements 6-8 OR, the first elements AND 9- 11, RS-flip-flops 12-14 and the second elements 15 and 16 AND, additional triggers 17 and 18, element 19 2И-OR and element 20 ЗИ-OR, one input of the first delay cell 1 - I is connected to the input bus, another input the first delay cell 1 - I and the input of the K-th delay cell - -K are connected to the outputs of switch 5 (with elements 16 and 15 AND responsible), the input of one or several delay cells and the installation inputs O of the flip-flops 2, 3, 17, 18, 12, 13, 14 are connected to the source of the reference signal, the counting inputs of the flip-flops 2 and 3 are connected to the outputs of the first 1 - 1 and K-th 1-K delay cells, outputs trigger 2 and 3 are connected to element 4 AND, the outputs of delay cells 1 - 1, 1-2 ... 1-n are connected to the inputs of elements OR 6-8 of switch 5, and one of the inputs of elements AND 9, 10, AND, 15, 16 - to the information signal bus, the inverse output of the trigger 12 of one channel of the switch 5 is connected to the inputs of the elements 10 and 11 of the other two channels of comm triggers 13 and 14 are connected in the same way. The direct outputs of triggers 12-14 of switch 5 are connected to the inputs of element 20 ZI-OR, the input of the first element I of which is connected to the output of element 19 2I-OR, the input of the second logical element AND - with the output of the main element 4 And the input of the third logical element And with the output of trigger 2 and with the counting input of the first additional trigger 17, the outputs of which are connected to the inputs of the element 19, 2I-OR, the other inputs of the element 19 2I-OR are connected to the outputs of the second additional trigger 18, score whose first input is connected to the output of the main trigger 3.

Works shaper time interval as follows. As an example, take p 8,

 ......, 1-h-g,

where t is the duration of the pulse generated by the delay cell, t is the time

About restoring delay cells.

The initial state of the imager, defined by the reference signal Ue, explains the time interval O - to on time diagrams (Figs. 2, 3).

With the arrival of the information signal UM, the leading edge of which corresponds to the beginning of the memorized time interval, the first delay cell 1-1 starts up, from the trailing edge of which the remaining delay cells 1-2 ... 1-П are sequentially started (diagrams U | -U) Information signal UA ,, whose leading edge corresponds to the end of the memorized time interval, is fed to the input of switch 5, which, depending on the time of arrival of this signal (the duration of the memorized time interval), triggers the first 1 - 1 (O, . 2) or a K-th 1st To (Ux in FIG. 3) and the delay cell output line connects to a corresponding output signal generating circuit. The ring circuit of the I series-connected delay cells 1 - l ... l-n enters the generation mode (diagrams U / -U / in Figs. 2 and 3), exactly reproducing the time interval (t (-tc) fixed at its inputs).

 By means of switch 5, triggers 2,3, 17, 18 and element 4 I, element 19 2I-OR, the spurious signal resulting from the generation is suppressed and the desired signal is extracted.

jj To understand the technical nature of the proposed driver, we consider three cases.

.2T.

In this case, from the information signals of the AI (, and the first 1-1 and 2-a 1-K delayed cells are triggered, the output signal is generated at the output of element 4 I. A special feature is that the information signal & 2 comes to input elements 9, 10, 11, 15, 16 I. Pass element 10 I (the one to which input element 7 OR is connected) connected to the output of the first 1 - 1 and second 1-2 delay cells triggers RS flip-flop 13 , forming a high potential at the forward output (signal Ue in Fig. II, allowing the signal to pass from the output of element 4 AND through element 20 ZI-OR to the device output. Simultaneously with the signal from the inverse arm

the trigger 13 prohibits the triggering of the triggers 12 and 14, which prohibit the passage of signals from the output of the trigger 2 and from the output of the element 19 2I-OR to the output of the device.

2, -,.

in this case, the information signal Uexa through element 11 I, to the input of which element 8 OR is connected, connected to the outputs of delay cells 1-3 ... 1-6, triggers trigger 14, which generates a signal of the SL (Fig. 1), allowing restart signal Uex2. Delay cells 1 - 1 and passing to the output of the device signal Ua, formed by trigger 2 (signals., It, and a Uewx in Fig. 1 and 2). At the same time, the inverse signal from trigger 14 prohibits the triggering of other triggers 13 and 12, which prevent the issuance of false information.

in this case, the information signal and, through element 9 I, to the input of which element 6 OR is connected, connected to the outputs of delay cells 1--7, 1-8, triggers trigger 12, which generates an id signal (see Fig. 1), allowing the UeX2 signal to trigger 1-k delay cells and passing to the device output signal from the output of element 19 2I-OR (Fig. 1 and 3).

At the same time, the inverse signal from trigger 12 prevents the triggering of other triggers 13 and 14.

The performance of the imager clearly explains the time diagrams, where the ratio of the maximum duration of the memorized time interval (t / -to) / nax to the generation period T is 1.

The speed of the known former is determined by the number of delay cells connected between the first and K-th delay cells, and for the delay cells, i; i. and 4 1, i.e., the same as in the proposed former, is associated with a colic delay cell and the expression n -.- t-, where f iij fiiax is a coefficient characterizing the speed of the device. Or (1 -, m., E. F 1 with n,

which is practically not feasible.

Claims (2)

1. Shaper time interval for auth. St. No. 496660, characterized in that, in order to improve speed, two additional triggers with a counting input are introduced into it, elements 2I 0 OR, ZI-OR and the switch, the inputs of which are connected to the outputs of the delay cells and the input and reference signals, control outputs to the inputs of the 1st and K-th delay cells, logical outputs5 to the inputs of the ZI-OR element, the input of the first element And which is connected to the output of the element 2И-OR, the input of the second element And - with the output of the main element And, the input of the third element And - with the output of the first main trigger and with the counting 0 input of the first additional trigger, the outputs of which are connected to the inputs of element 2И-OR, the other inputs of which are connected to the outputs of the second additional trigger, the counting input of which is connected to the output of the second main trigger, and the installation input O to the installation O of the first additional trigger and to the reference signal bus. 2. The former according to claim 1, characterized in that the switch comprises three channels, each of which consists of the OR connected in series, the first AND, the RS flip-flop and the second AND, and the R-inputs T4) of the igger are connected and connected to reference bus, inverse trigger output of one channel 5 is connected to the inputs of the first AND elements of the other two channels, the forward outputs of the flip-flops are the logical outputs of the switch, the outputs of the second AND elements of the two channels are OR-connected, and all other AND elements are interconnected via one input. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 496669, cl. H 03 K 5/153, 03.06.74. , l te t fi lput.3