SU822287A1 - Buffer storage - Google Patents

Description

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This invention relates to memory devices.

Known buffer memory device 1 and p.

One of the known devices contains a cumulative block, an address register and a control block, an input register, a message source, a computation block, two counters, two AND schemes, a group of OR schemes, two decoders, and a local control block consisting of local record and read blocks. .

A disadvantage of this device is its low speed.

The closest technical solution to the proposed. is a 6U farm memory device comprising a pulse generator, an input register, a RAM memory unit, a control unit, two AND groups, OR elements, write and read address counters, an address decoder, and an output / pfj register.

The disadvantage of this device is that it has a write and read speed two times lower than the maximum possible memory used in this device.

which significantly reduces its speed.

The purpose of the invention is to increase the speed of the device .:

The goal is achieved in that a buffer memory device containing a drive, input and output registers, four groups of AND elements, a decoder, counters of write and read addresses, and a group of OR elements, the inputs of the input register being connected to the input buses of the device, and the outputs with the first inputs of elements AND of the first group, the outputs of which are connected to the information inputs of the storage device, the information outputs of which are connected to the first inputs of the elements AND of the second group, the outputs of which are connected to the inputs yhodnogo register, the outputs of which are connected on the output device tire, the first inputs of OR elements of the third and fourth groups are connected respectively to the outputs of the counter and write address. the read address counter, and the outputs, respectively, to the first and second inputs of the OR elements, the outputs of which are connected to inputs of the digital amplifier, the outputs of which are connected to the address inputs of the storage device, are entered three triggers, four AND elements, an OR element, a single generator impulses, a waiting pulse generator and three delay elements, the input of a single impulse generator 1 is connected to the output of the OR element, and the outputs to the first input of the first trigger and tiepBOMy to the drive control input, the first inputs of the first and second elements And are connected to the control inputs of the device, and the outputs are respectively with the first inputs of the second and third flip-flops, the second inputs of which are connected to the outputs of the first and second delay elements, respectively, the first output of the second trigger is connected to the first and third groups and the first input of the third element And, the output of which is connected to the input of the first delay element, the second output of the second trigger is connected to the second control input of the accumulator by the second input of the second element And, the first, input IDNs and the input of the write address counter, the first output of the third trigger is connected to the second input of the OR element, the input of the read address counter, the second input of the first AND element, and the third. the second inputs of the third and fourth elements And, the output of the first trigger is connected to the input of the waiting pulse generator, the output of which is connected to the third input of the first element And and the input of the third delay element, the output of which Wow is connected to the third input of the second element I.

The drawing shows a functional diagram of the proposed device.

The device contains a drive 1, which represents an operational memory, a waiting generator 2 pulses first 3, second 4 and third 5 triggers, input register 6 with input buses 7, first 8 and second 9 elements And, first 10 and second 11 groups of elements And , element OR 12, generator, 13 single pulses, deshlrator 14, counter 15 write addresses, group 16 elements OR, third 17 and uvert 18 elements AND, first 19, second 20 and third 21 delay elements, third 22 and quarter 5 10 23 groups I items, 24 read address counter, output register 25, output shi us 26.

The inputs of the input register 6 are connected to the input buses 7 of the device, and the outputs to the first inputs of the elements AND of the first group 10, the outputs of which are connected to the information inputs of the storage device 1. The information outputs of the storage device 1 are connected to the first inputs of the elements AND of the second group 11, the outputs of which are connected to

the inputs of the output register 25, the outputs of which are connected to the output tires 26 of the device. The first inputs of the third and third 22 and fourth 23 elements are connected respectively to the outputs of the counter 15 write addresses and 24 read addresses counter, and the outputs respectively to the first and second inputs of the OR elements of group 16, whose outputs are connected to the inputs of the decoder 14. Decoder outputs 14 connected to address inputs of accumulator 1. Generator input of 13 single pulses is connected to the output of element OR 12, and the output is connected to the first input of the first trigger 3 and the first control input of the accumulator 1. First inputs of the first 8 and second 9 elements Tov and connected to the control device kntsimi inputs and outputs - respectively to the first inputs of the second 4 and third 5 triggers -sec inputs are connected to outputs of the first 19 and second delay elements 20 respectively. The first output of the second trigger 4 is connected to the second inputs of the elements And the first 10 and third 22. groups and the first input of the third element And 17, the output of which is connected to the input of the first delay element 19. The second output of the second, trigger 4 is connected to the second control input of the accumulator 1, the second input of the second element AND 9, the first input of the OR element 12. and the input of the counter 15 write addresses. The first output of the third trigger 5 is connected to the second input element And the second 11 and fourth 23 groups and the first input of the fourth element And 18, the output of which is connected to the input of the second delay element 20. The second output of the third trigger 5 is connected to the second input of the element OR 12, the input of the read address counter 24, the second input of the first element AND 8, and the third control to the circuit. I drive input 1. The second input of the first trigger 3 is connected to the synchronization output of the drive 1 and the second inputs of the third 17 and fourth 18 elements I. The output of the first trigger 3 is connected to the input of the waiting generator 2 pulses, the output of which is connected to the third input of the first element And 8 and the input of the third element 21 of the delay, the output of which is connected to the third input of the second element And 9.

The device works as follows

Claims (2)

1. USSR author's certificate number 378832, cl. G 06 F 3/04, 1970. 2. USSR author's certificate number 515154, cl. G 11 C 9/00, 1974 (prototype).