SU811218A1 - Interpolator - Google Patents

Abstract

An interpolator containing a reversible counter, the first inputs of which are connected via a key block to the outputs of the first register and connected in series to a pulse generator, the first counter, the pulse driver unit, the first block of AND elements and the first OR element whose output is connected to the second input of the reversible counter, differing in that, in order to expand the functionality of the interpolator, a second register, a second block of AND elements, a second OR element, a second counter, and b comparison unit, the second inputs of which are connected to the outputs of the reversible counter, and the output - with the first input of the pulse generator, the second input of which is connected to the first input of the device, and the third input - to the second inputs of the first counter and the first and second registers and to the second input of the device, moreover, the second inputs of the second block of elements And are connected to the outputs of the block of pulse shapers.

Description

The invention relates to automation and computing and can be used in radio communication devices, telemechanics, telegraphy, in particular in a digital frequency detector to accurately calculate the modulation moment.

A device is known for interpolating the values of a function y of an independent variable x, comprising first and second registers for storing finite values of a range of values of a function and a control unit for controlling operations in a sequence of cycles.

The closest technical solution is a device that generates at its output a voltage that varies linearly in time from 0 to some given value A during a fixed time interval T, called a clock, i.e. I

A00

allows computation of functions of the form Z t,; .

where t is the current time measured from the moment the device starts operating.

The disadvantage of this device is that it does not allow calculating the values of functions of the form Z K. . "- , what

/ L i d

significantly narrows its scope.

The aim of the invention is to expand the functionality of the device by using it to calculate the value of the functions of the form Z-K A A + B

The goal is achieved by the fact that in the device containing the reversible counter, the first

the inputs of which are connected via a block of keys to the outputs of the first register, - and a pulse generator connected in series, the first counter -cc, the pulse driver block, the first block of 1/1 elements and the first OR element, whose output is connected to the second input of the reversing counter, are connected in series the second register, the second block of elements V. the second OR element, the second counter and the comparison block, the second inputs of which are connected to the outputs of the reversible counter, and the output to the first input of the pulse generator, the second input otorrhea connected to the first input device of the input to the second inputs of the first estimator and the first and second registers and to the second input device, the second-block and the second inputs of AND gates with outputs soediieka pulse shaping block.

The registers are intended to store the numbers A L B, respectively, for the duration of the computation of the value of the functions, which are whole binary numbers without a sign. Time counter is intended for; for measuring the time of operation of the device from the start of its startup until the moment of shutdown and the formation of a computational value Zn. Fu., Z. The key block is designed to control the time of the transfer of the city of the register of the reversible counter, G, 1111-1k time | intervals, register, fsrME / pulpers of pulses, the first elements of T and L of the first element OR form a sequence YampulsoB with a frequency proportional to the number A, and periiCTp, the second elements AND, the second element OR, a counter of time interval, alov t for W W, the pulse generator form a sequence pulses with a frequency proportional to the B.R.V. number the counter performs the reading from the number of 1pulses previously entered into it, arriving at its subtracting input from the output of the first element IL1 / 1. Second

the counter performs the summation of pulses arriving at its counting input from the second element OR, the Comparison Unit is designed to compare the contents

a counter for issuing a signal to one of the entrances of the Ostzio generator at the moment of their equality; In the initial position, the counters and registers are in the zero state, and the generator is inhibited, which is achieved by applying a device installation signal to the initial state at its input,

At the beginning of the cycle of operation of the device by supplying the corresponding control signals 8, the registers are entered into codes of numbers A and B

accordingly, after which the code of the number A is rewritten into the reversible counter. Then, the generator is started by applying a control signal to its input. From the generator output, the pulses go to

counting the counter until the signal from the number comparison unit to one of the generator's stop inputs stops it. The current value of the number in the up-down counter (yi) changes when

this is according to the law yi А - -тт х, where x is flow 1, its

the value of the number in the first counter, and K - its capacity. The current value of the number in the second

- .,AT

the counter (ya) is varied according to the law y2-gx,

TO

at the moment of comparing the current values of the number in the reverse and second counters, the first counter will record the number determined from

ABI A

x: X Z k -, - V V с ::; g :: I,

k

A + B

t, e, the proposed device allows to calculate the value of functions of the form g k

BUT

A + B

The effectiveness of the invention lies in the simplicity of building on the basis of the device proposed — digital frequency detectors. working in harsh climatic conditions and having a small suit Ken1 / with a low carrier frequency.

Claims (1)

An INTERPOLATOR, comprising a reversible counter, the first inputs of which are connected through the key block to the outputs of the first register, and series-connected pulse generator, the first counter, the pulse shaper block, the first block of AND elements and the first OR element, the output of which is connected to the second input of the reverse counter, different the fact that, in order to expand the functionality of the interpolator, a second register, a second block of AND elements, a second OR element, a second counter and a comparison unit, the second inputs of which are connected to the outputs of the reversible counter, and the output is connected to the first input of the pulse generator, the second input of which is connected to the first input of the device, and the third input to the second inputs of the first counter and the first and second registers and to the second input of the device, moreover, the second inputs of the second block of elements And are connected to the outputs of the block of pulse shapers.