SU809351A1 - Device for writing information into shift register - Google Patents

Description

The invention relates to a pulse technique and can be used in the equipment for processing discrete signals. There are known schemes for writing pulses to a register, containing R-S type triggers and logic circuits and C3. A disadvantage of the known devices is that information pulses are guaranteed to be written into a register with a minimum alignment on the leading edges equal to 1.5-2 periods of clock pulses. The closest in technical essence to the present invention is a device for recording information in the region of the |; t shift, containing n Dt flip-flops, an AND-NOT element and a group of I-NOT elements, synchronization inputs 1, Dt flip-flops are connected to the device input, Dt flip-flops - to the input of the NAND element, the output of which is connected to the input of the shift register, the i-th output of which is connected to the corresponding inputs from i to n elements of the IS-NOT group (, 3,.,. P), outputs to e € sHTOB AND-NOT groups are connected to the input of the installation of the corresponding one and the input of Dt after that, a trigger c, the first register output is connected to the input of the first NAND element of group L4. A disadvantage of the known device is the complexity, since in order to guarantee that the pulses in the shift register are n pulses, following with the arrangement equal to the period of the register clock pulses, the arrangement must contain n Dt triggers and (n + 1) AND-NOT elements. The purpose of the invention is to simplify the device. The goal is achieved by the fact that in the device for recording information in the shift register containing the LC-trigger, the element AND-NOT, the RS-trigger, the hero and clock buses, the output of the jK-trigger is connected to one of the inputs of the element AND-NOT, the other input element AND-NOT connected to the first clock bus, the output element AND-NOT connected to the S-input of the RS-flip-flop, the R-input of which is connected to the second clock bus, output of the RS-flip-flop is connected to the output of the device. EK-trigger, 3-input of which is connected to the input of the device. i FIG. 1 shows a functional diagram of the proposed device;

in fig. 2 - time diagrams of the device.

The device contains a JK-flip-flop 1, element 2 AND-NOT, RS-flip-flop 3, input 4 of the device, clock buses 5 and 6, output 7 of the ZK flip-flop 1, output 8 of the element 2 AND-NOT and output 9 of the RS-flip-flop 3

The device operates as follows.

In the initial state at the moment of time to (Fig. 2} at the direct output 7 of the trigger 1, the voltage level at the output 8 of the element 2 is high, the output 9 of the trigger 3 is the device output - high voltage due to impact on R-vhrd trigger 3 low level with input 6.

When the input impulse trigger 1 arrives at the time t at the device input 4 (the L input of the trigger 1) triggers and a high voltage level is set at its output 7, which, when it enters the input of the element 2, prepares it for operation.

At time tj, when a high level voltage element 2 arrives at the other input, input 5 lowers the voltage level at its output 8, which, arriving at the S input of the trigger 3, prepares it for switching.

At time t, a high voltage level arrives at the R input of trigger 3 from input 6, which, entering the K input of trigger 1, sets the latter to its initial state (at output 7 of trigger 1, a low voltage level is set) those. trigger 1 is ready to receive the next input pulse. The low voltage from the output 7 of the trigger 1, entering the input of the element 2 sets at its output 8 a high voltage level, which, entering the S-input of the trigger 3, prepares it to switch to the initial state.

At time t, a low voltage level is established at the input R of the flip-flop 3, the flip-flop 3 switches and a high voltage level appears at its output 9 (device output).

when entering jity, ty at input 4 devices

input pulse output device 9 at times t.t-. corresponding pulses appear that are tied to a clock frequency T l with a duration equal to the duration of the clock pulse on input 6.

The construction of a device for recording information into the shift register according to the proposed scheme allows, with a significant reduction in the volume of the device, to process peak-free pulse densities, for example, under the effect of interference, without gaps. So, if necessary, process a pulsed message of three pulses,

following with an interval equal to the period of clock pulses, the known device must contain three O flip-flops, four AND-NOT elements and 19 links, while the proposed

device contains two triggers

(J-K and R-S), the element AND-NOT and 7, connections.

With an increase in the required number of processed pulses, the gain in the amount of equipment and the number of connections increases even more.

Claims (4)

1. USSR author's certificate number 410547, cl. H 03 K 5/13, 1974. 2. USSR author's certificate number 448585, cl. H 03 K 5/13, 1974. 3. USSR author's certificate No. 474051, cl. G11 19/00, 1975. 4. USSR author's certificate  617787, cl. G11 C 7/00, 1978 (prototype). t, ti tj tfie T "I (fat. I tf