SU807318A1 - Multichannel device for solving systems of linear algebraic equations - Google Patents

Description

The invention relates to computing and can be applied in the construction of specialized and problem-oriented processes for solving systems of linear algebraic equations (SLAE). A known digital device for solving systems of equations built on the basis of integrators and containing integrators of coefficients, integrators of free member and integrators unknowns, and the / outputs of the integrators of the coefficients of each column are connected to the inputs of the integrators of the free term of the same column, the outputs of which are They are connected to the inputs of unknown unknowns of the same column and the inputs of the integrators of the coefficients of the corresponding rows. The disadvantages of this device are a large amount of equipment due to the presence in the device of complex integrator units and low performance, because the integrators have inertia and instead of the original algebra. equivalent differential equation with a long time to reach steady state. A digital device for solving a SLAE is also known, containing registers of a free member, registers of unknowns, adders, multipliers, coincidence circuits,. comparison circuits and reception circuits 2. A disadvantage of this device is a large amount of equipment, since it contains a large number of complex blocks such as adders, multipliers. The closest in technical essence to the present invention is a device comprising adders, reversible counters, shift registers, control inputs of the shift registers are connected to the control bus, and the outputs are connected to the first inputs of the corresponding adders combined in n-columns and n-connected in series single adders, control inputs of single-digit adders of each row are connected to the input of the corresponding reversible counter, analysis unit, AND, OR elements, output of the n-th single-digit adder each column is connected to a first input of OR, OR element output coupled to an input of (n + 1) -th

shift register, the output of the sign bit (n + 1) -th shift rep JTpa is connected with the first input of the analysis unit, the output of which is connected to the input of the corresponding reversible counter, the output of the (n + 1) -th shift register is connected to the second input of the analysis unit and through the first element I with the second input of the element. OR and with the second input of the first one-digit Totalizer of the corresponding column, the second, the inputs of the AND elements of all the columns and the control inputs of the reversible counters are connected to the control bus 3.

The purpose of the invention is to expand the functionality by implementing an algorithm that does not depend on the coefficients of the matrix of the system of equations,

The goal is achieved by the fact that the device containing a memory block in the channel, the first group of outputs of which is connected to the inputs of the first adder, the output of which is connected to the input of the first trigger and the reversible counter, through the encoders of the first group, a second trigger is inserted into each channel. and the second, a group of encoders, the outputs of which are connected to the inputs of the second adder, the output of which turns the second trigger connected to the input of the reversible counter and the inputs of the encoders of the first group, the first inputs of the cipher The second inputs of the second group of encoders are connected to the outputs of the first triggers of the corresponding channels, the outputs of the first triggers are connected to the input of the first adder of the corresponding channel.

The drawing shows a schematic of the device.

The device contains 1 memory blocks, adders-2 and 3, reversible counters 4, triggers. 5 and 6, encoders. 7 and 8,

The device works as follows.

In the first blocks of 1 memory, the codes of the coefficients of the solved SLAE are entered ,. adders 2 put free member codes, and adders 3 and reversible counters 4 are set to the zero state. The triggers 5 are set to the state corresponding to the sign of the trace, calculated in adders 2 (in the first iteration it is the sign of the free term M-). From blocks 1 of the memory, through the encoders 8, controlled by signals from the flip-flops 5, the coefficients of the corresponding columns of the SLAE matrix with a shift of 6 bits to the left are fed to the inputs of the adders 3

(С 1 - Р, Р is the resolution), i.e. in adders 3, the values of the residual are calculated according to the following formula

5, a, jU, i “V,

cKfl

where - the value of nevoc in the adder 3 on the previous iteration

U.J- - signals of the state of the flip-flops 5, corresponding to the signs of the constraint t in adders 2; J

,if a

G if ewVo;

q is the basic numbering system; fW- value of the residual in adders 2.

From memory blocks 1 through the encryption 0, controlled by signals from flip-flops b, the calculation inputs of adders 2 receive the coefficient codes of the corresponding rows of the SLAE matrix with a shift to E bits to the left (E 5 other subtraction inputs of adders 2 receive C-th bits) in accordance with the signs of the fixed key, fixed in the triggers 5, i.e., in the adders 2, the values of the fixed block are calculated in accordance with

the following formula

.jUifc, -4M

- - the value of the residual in adders 2 on the k-th iteration;

.

fJtl trigger state signals. 6, corresponding to the signs of the threshold € .J in the adders 3;

-AND

6 SLM,

iflm

. At the same time, in the reverse meters 4, the codes of unknown unknowns are formed according to the following dependencies

Y (+ - |) a-2 0, - -f + U, j- q,

those. in the 6th position of the reversible counters 4, a unit is added or subtracted, depending on the state of the triggers 6. Codes of row coefficients .- (1,2 ... ,, n)

The solved system of equations d b (i 1,2 ,,., п) is stored in the respective memory blocks. Before solving the problem, adders add free codes to the adders, and the reversible counters are set to the zero state. At the first iteration, the signs of the free members are fixed in the triggers, then the codes of the coefficients of the corresponding lines shifted by t bits (B 1 -) are added to the codes contained in the adders and the 5 remaining ones for the first iteration. P, where P is the width of the representation of the numbers in the device) in the direction of the younger ones - P5 DOV.

At the same time, in the 6th digit of the reversible counters, one is added or subtracted depending on the state of the triggers, i.e. in accordance with the signs nevzok. On each (k + 1) -th and-hierack calculation, the nez in the adders is made in accordance with the formula

p (), ck. W i -i :( G where .q is the base of the number system; and is the state of the triggers 5 tta

k-oh inter.atsii, moreover, .1 - - (if O,

 + -1 if €. about.

The calculation of the unknowns that are unknown at (k + 1) -th iterations is performed by the formula

H.K + 1 + Uf .q "

The method of simple iteration for solving the SLAE, one of the modifications of which is the algorithm implemented in the device, converges, if the coefficients of the solved SLAE satisfy the following conditions aiil .2, i.e. the diagonal coefficients of the solved SLAE are larger than the absolute value of the sum of all the other coefficients in a row or column of the coefficient matrix 1. However, the wide class to which the problems arising in applied mechanics (in the processing of experimental information / determination of correlation coefficients) in problems of the theory of sex are reduced; and mathematical physics and some other scientific and technical problems do not satisfy the above limitations and the coefficients in the diagonal of the matrix are smaller in absolute value of the other coefficients in a row or column. Such problems cannot be solved in a known device.

The proposed device implements such an algorithm, which does not depend

| from the coefficients of the SLAE matrix; therefore, the device approaches in its capabilities the mainframe computer as part of the SLAE solution, but has higher performance and efficiency of information processing, which allows realizing fast and cheap computing devices and using ah in real-time information processing systems of time.

Claims (3)

1.F.Mayorov. Electronic numbers 5 level integrating machines, M., Mashgiz, 1962, p. 86-88. 2. Evreinov E.V. and Prangishvilm I.V. Adjustable structure digital automat {homogeneous 0 environment), m ;, Energie, 1972, p. 195. 3. Authors certificate of the USSR 543943, cl. G 06 F 15/32, .1975 (prototype).