SU1290299A1 - Arithmetic unit - Google Patents

Abstract

The invention relates to the field of computing and can be used for pipelining of arrays of numbers. The aim of the invention is to reduce equipment costs. The goal is achieved by the fact that an arithmetic unit containing an AND element and computational blocks, each of which contains three registers, an adder-subtractor, a trigger, an OR element, two EXCLUSIVE OR elements, three switches, two AND elements and the NOT element, contains EXCLUSIVE SHS element with corresponding links. 1 il. (Ls

Description

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The invention relates to computing and can be used in the construction of computing devices for performing multiplication, division, and extraction of the square root when processing arrays of multi-digit numbers.

The purpose of the invention is to reduce equipment costs.

The drawing shows a diagram of the 0 arithmetic device.

The arithmetic unit contains computing blocks 1, each computing block 1 contains trigger 2, first, second and third registers 3, A and 5, the first element is EXCLUSIVE OR 6, the adder-subtractor 7, the second element is EXCLUSIVE 01EEE 8, the first and the second elements And 9 and 10, the element OR 11, the element NOT 12 ,, the first, second and third switches 13, 14 and 15, the input 16 clock pulses of the device, the first, the second and third information inputs 17, 18 and 19 of the device, the input 20 square root device retrieval, device 21 multiplication input, device division input 22 Twa IdHM XOR element 23, AND gate 24, the first, second and third informational outputs 25, 26, 30 and 27 of the device.

The arithmetic unit works as follows.

In the initial state, the informational 17, 18, and 19 and the control 20, 21, 3.5, and 22 inputs are at zero.

In the multiplication operation, a unit potential is applied to the multiplication input 21, and a zero potential is applied to the inputs 20 and 22 of the extraction of 40 square root and division.

The multiplicand and the multiplier sink down respectively to the second and third informational inputs 18 and 19 of the device, and to the first information input I 7 of the device, at the same time, a zero potential drops down.

A zero potential is fed to the third control input of the switch 14 from the output of the element OR 11.

On the first clock pulse, one is recorded in the trigger 2 of the first computing unit 1, and multiplied in the multiplier at 55. In every computational

sets the calculator 7 operation subtraction.

The values of the nth and (n 1) th bits of the multiplier are fed to the inputs of the EXCLUSIVE OR 6 element, on the forward and inverse outputs of which, respectively, single signals are formed when these bits are unequal.

The infurmation from the outputs of the IC KEY NO. 6 element passes through the elements 9 and 10 and enters the first and second control inputs of the switch 14.

Depending on the values at the first and second control inputs, the output of the switch 14 is transferred offset by one bit of information from in the course of the register 3 or the adder contains the body 7 "

Information from the output of the second commutator i 4 of the first computational cca 1 is fed to the input of the first register 3 ((the oldest bits) and to the input, the first discharge of the third register 5 ((n + 1) -and discharge) of the second computational unit one ,

On the remaining inputs of the third register 5 of the second computing unit W

the multiplier C comes from the third register 5, shifted to the right by one bit. The value of the h-th bit of the multiplier passes through the first switch 13 and is fed to the information input of the trigger 2 of the second computing unit 1. The second register 4, multiplied from the outputs, except for the second and third bits, is fed to the inputs of the corresponding bits of the second register of the second computing unit 1.

The second and third bits of the multiplier pass through the third switch 1 to the inputs of the second and third bits to the second register of the second computational unit 1.

The second clock pulse of information from the outputs of the first computing unit 1 is recorded in a trigger.

2, first, second, third register

3.4 and 3 of the second computational block C. At the same time, in the first computational unit 1, new information is recorded to execute the operation

The second, second, and third registers 3, 4, and 5 of the same computational block are, respectively, Zero, multiplicand and resident. Trigger 2 output signal

0

five

0

50

.five

0

five

0

5 multiply. In every computational

sets the calculator 7 subtraction operation.

The values of the nth and (n 1) th bits of the multiplier are fed to the inputs of the EXCLUSIVE OR 6 element, on the forward and inverse outputs of which, respectively, single signals are formed when these bits are unequal.

The infurmation from the outputs of the IS-KEY NO. 6 element passes through the elements 9 and 10 and enters the first and second control inputs of the switch 14.

Depending on the values of the first and second control inputs, the output of the switch 14 is transferred shifted by one bit the information from the output of the register 3 or the adder-reading 7 7

Information from the output of the second switch i 4 of the first computing unit 1 is fed to the input of the first register 3 ((older bits) and to the input, the first bit of the third register 5 ((n + 1) and bit) of the second computing unit 1,

On the remaining inputs of the third register 5 of the second computing unit 1 W5

enters the multiplier C of the third register 5, shifted to the right by one bit d. The value of the h-th bit of the multiplier passes through the first switch 13 and is fed to the information input of the trigger 2 of the second computing unit 1. The multiplier from the outputs of the second register 4, except for the second and third bits, is fed to the inputs of the corresponding bits of the second register 4 of the second computational unit 1.

The second and third bits of the multiplicand passes through the third switch 15 to the inputs of the second and third bits of the second register of the second computing unit 1.

On the second clock pulse, information from the outputs of the first computing unit 1 is written to the trigger.

2, first, second, third registers

3.4 and 3 of the second computational unit C. At the same time, in the first computational unit 1, a new information is recorded to execute the operation

the block performs one integration of the multiplication algorithm. The result of multiplication with double precision is removed from the outputs of the second switch 14 and

third register 5 computing unit Ij.

In the division operation by input, 22 divisions are given a single potential, and a zero potential is applied to inputs 20 and 21 of the square root and multiplication. ,

Older digits of the dividend (first half word) arrive at the first input 17 of the device, and its younger bits (second half word) arrive at the third information input 19 of the device, with the lower bit of the second half word arriving at the input of the first discharge of this information input. The divider is fed to the second information input 18 of the device.

The sign bits of the dividend and the divider are fed to the inputs of the element EXCLUSIVE OR 23 | the signal from the output of the k-20 mutator 15 and enters the inputs of the corresponding passes through the element AND 24 and, with equality of 3 characters, sets the trigger 2 of the first computing unit to one.

On the first clock cycle, the pulse of the intuit unit 1 is recorded in the trigeneration from the information inputs 17, 18 and 19 of the device is recorded in registers 3, 4 and 5 of the first computational unit 1, the subtractor 7 of which performs 30 subtraction or summation at respectively single or zero trigger 2.

The inverse sign of the result, obtained at the output of the adder-5 subtractor 7, is fed to the second input of the second element EXCLUSIVE RSHI B, the first input of which receives the sign of the divisor.

In the case of equality of information at 0, the first and second inputs of the second element EXCLUSIVE OR 8 at the output of this element, we get zero, and in the case of inequality - one. Information from the output of the second element EXCLUSIVE 5 OR 8 passes through the first switch 13 and is fed to the input of the trigger 2 of the second computing unit,

ger 2, in the first, second and third registers 3, 4 and 5 of the second computing unit 1 ,. At the same time, new information is written to the first computing unit t to perform the division operation. In the computational block, one division algorithm is executed. The result of dividing C from the outputs of the (h -) -th bits of the third register 5 and (h + 1) -th bit of the second switch 14 of the computing unit 1, and the information at the output of the (and-1) -th bit of the third register 5 is the sign of the result, and output information

(h + 1) -th bit of the second switch - the youngest bit after passing the data (x through all the computing blocks 1.

When extracting the square root to the input 20, a unit potential is applied, and to the inputs 21 and 22 of multiplication and division, a zero potential is given. Older

The information from the adder subtractor 7, shifted to the left by one bit, passes through the second switch 14 and enters the inputs of the higher bits of the first register 3 of the second computational unit.

The input to the low-order bit of this register 3 receives information from the output of the h-th bit of the third register 5 of the first computational unit, through the corresponding bit of the second switch 14 of this computational unit. Information from the output of the (+) -th bit of the second switch 14 (private sign} goes to the input of the first bit of the third register 5 of the second computing unit 1j. The inputs of the remaining bits of this register 5 receive information from the outputs of the third register 5 of the first computing block 1 ,, shifted to the right by one bit. The divider from the output of the second register 4, except for the second and third bits, is fed to the inputs of the corresponding bits of the second register 4 of the computing unit 1, Information from the outputs of the second and third bits of the second Register 4 passes through the third corresponding bits of the second register 4 of the second computing unit 1.

According to the second clock pulse, the information from the outputs of the first number 2, to the first, second and third registers 3, 4 and 5 of the second computational unit 1 ,. At the same time, new information is written to the first computing unit t to perform the division operation. In the computational block, one division algorithm is executed. The result of dividing C from the outputs of the (h -) -th bits of the third register 5 and (h + 1) -th bit of the second switch 14 of the computing unit 1, and the information at the output of the (and-1) -th bit of the third register 5 is the sign of the result, and output information

(h + 1) -th bit of the second switch - the youngest bit after passing the data (x through all the computing blocks 1.

When extracting the square root to the input 20, a unit potential is applied, and to the inputs 21 and 22 of multiplication and division, a zero potential is given. Older

the bits of the radicand (the first half-word) arrive at the first information input 17 of the device, the lower bits (the second half-word) go to the third information input 19 of the device,

Wich the younger bit of the second half-word goes to the input of the first bit of this information input. The second information input device 18 receives a zero. At the exit ele51

The unit is set at the input of trigger 2 of the first computational unit 1. The potential from the square root extraction input 20 goes to the installation inputs to the third, fourth, ..., (2) -th bits of the second registers 4, respectively, first, second 1 j, ..., i-ro computing unit and sets register bits 4 per unit.

On the first clock pulse, one unit is recorded in the trigger 2 of the first computing unit, and the second, third, and third registers 3, 4, and 5 of this computing unit receive information from the first, second, and third information inputs 17, 18, and 19 of the device, respectively. At the adder-subtractor 7, the contents of the second register 4 (0.010, .. P) are subtracted from the contents of the first register 3. The result of the subtraction, shifted to the left by one bit, passes through the second switch 14 and enters the inputs of the higher bits 3 of the second computational unit 1. The input of the least significant bit of this register 3 receives information from the output of the h-th bit of the third register 5 of the first computing unit, passing through the corresponding bit of the second switch 14 of this computing unit.

And :: the true value of the sign of the result of the subtraction, obtained at the output of the adder-subtractor 7, is fed to the second input of the second element ISKHSHOCHA-YULLEYE OR 8, the first input of which receives zero from the output of the first bit of the second register 4. In case of equality of information on the first and the second input of the second element EXCLUSIVE OR 8 at the output of this element receive zero, and in the case of inequality - one. The output of the second element EXCLUSIVE OR 8 passes through the first switch 13, through (h + 1) -and the bit of the second switch 14 and is fed respectively to the input of the trigger 2 and to the input of the first bit of the register 5 of the second computational unit 1. The information from the outputs of the second register 4, except for the second and third bits, is fed to the inputs of the corresponding bits of the second register A of the second computational unit 1 ,. On the second and third bits of this register post

902996

respectively, the inverse and my value of the sign of the adder-subtractor 7, passed through the third switch 1 5.

5. Information from the outputs of the third register 5, shifted to the right by one bit, is fed to the inputs of the third register 5 of the second computational unit 1.

10 On the second clock pulse, the information from the outputs of the first computing unit 1 is written into the trigger 2, 3 of the first, second and third registers 3, 4 and 5 of the second calculator.

5th unit 1. At the same time, new information is written to the first computing unit 1 to extract the square root. In each computing unit, one iteration is performed.

20 square root extraction algorithm.

The result of the square root extraction is obtained at the outputs of the second register 4 of the computational unit 1 after the data passes through all the computational units 1.

Claims (1)

Invention Formula 30 An arithmetic unit containing the element And And p computational blocks {. N - the width of the operands, each of which contains three registers, adder-subtractor, trigger, 35 element OR, two elements EXCLUSIVE OR, switch, second switch, two elements AND and element NOT, the information inputs of the first, second and third registers of the first output unit of the digital unit are connected to the first, second and third information inputs of the device, the first information output of the device is connected to the first n-bits 45 outputs of the second switch of the last computing unit, bits, except for the junior second information output of the device, are connected respectively to the first p-1 bits 50 third exit last the computational unit, the division input of the device is connected to the first input of the element I, the inverse output of which is connected to the information input of the trigger of the first computational unit, i and bit, (1 1, ..., the output of the third register of the i-th computational unit connected to the (i + 1) th digit of the information input of the third register (i + Ij-th computing unit, h of the first bits of the output of the second switch i-ro computing block connected to the information input of the first register (i + Ij -th computing block, output of the first switch of the i-th computing block connected to the information input of the trigger ( i + Ij of the computing unit, the device clock inputs are connected to the trigger enable inputs of the first, second and third registers of each computer unit, the device extracting the square root of the device is connected to the first control After it enters the third switch of each computing unit, the multiplication input of the device is connected to the first inputs of the first and second And elements and to the first control input of the first switch of each computing block, the output bits of the third switch of the i -th computing block are connected (1} -m and (i + 2) -m bits of the information input of the second register of the {i + 1) -th computing unit, in the i-th computing unit the bit of the second information input and the n and bit of the third information input of the second switch are connected respectively to the first bit of the output of the adder-subtractor and to the “th bit of the output of the third register, the first and second controls, the inputs of the second switch are connected respectively to the outputs the first and second elements And, the second inputs of which are connected respectively to the inverse and direct turns of the first g element EXCLUSIVE OR, the first control input of the third switch 5 is connected through the element NOT to the second pack the equal input of the third switch, the first bit of the first information input of which is connected to the inverse first bit of the output of the adder-subtractor, the first and second bits of the second information input of the third switch are connected respectively to (i + 1) and m (1 +, 2) th bits of the output of the second register, characterized in that, in order to reduce equipment costs, it contains the element EXCLUSIVE OR, and the input division of the device is connected to the first input of the element KPI each output of the trigger is connected to the input control of the adder-subtractor, the first-30th computing unit, the first new information input of which connects the first and second information to the output of the first register, and the second information input from the output of the second register, the first information input of the first switch is connected to th bit of the output of the third register, and (n + 1) th bit, the outputs of which are connected respectively to the first and second inputs of the first element EXCLUSIVE OR, the first and second inputs of the second element EXCLUSIVE OR are connected respectively About with the first bit of the output of the second register and with the inverse first bit of the output of the adder-subtractor, 45 output of the device, bits, except for the second information input of the first (i + 1) -th and (i + 2) -th, output of the second-hand the switch is connected to the output of the second element EXCLUSIVE 111EEE, OR (the device’s inputs are connected to the first and second inputs of the EXCLUSIVE OR, respectively, the output of which is connected to the second input of the device AND, the younger bit of the second information output of the device is connected to the (n + 1) -th output switch second switch Entrance square root extraction apparatus connected to the second input of the OR gate of each computing unit, the output of the second register of the last computational unit is the third information the first register of the i-th computing unit is connected to the corresponding bits of the information input of the second f register (+}) -th computing unit, (h + l) -and the output of the second switch of the m-th sixth unit is connected to the low-order bit of the information input The third register — G) —and the output bit of the first register is connected to the ith bit of the first information input of the second switch, the first bit of the first information input of which is connected to the first bit of the output of the first register, the i –th bit of the second and third "; 5 ra { i + 1) -th computational block, informational inputs of the second com- puter, and in the ith computational unit of the mutator, respectively, are connected to the (i - 1) -m and (i + 1) -th bits of the output of the second element EXCLUSIVE OR connected to (.p + 1) -th bit of the second information input of the third the progress of the adder - subtractor first the bit of the second information input and the p and bit of the third information input of the second switch are connected respectively to the first bit of the output of the adder-subtractor and to the “th bit of the output of the third register, the first and second controls of the second switch are connected respectively to the outputs of the first and the second element And, the second inputs of which are connected respectively to the inverse and direct turns of the first r element EXCLUSIVE OR, the first control input of the third switch is connected through the element NOT to the second control the third input of the first switch, the first bit of the first information input of which is connected to the inverse first bit of the output of the subtractor, the first and second bits of the second information input of the third switch are connected respectively to (i + 1) -m and (1 +, 2) bits of the output of the second register, characterized in that, in order to reduce equipment costs, it contains the element EXCLUSIVE OR, and the input division of the device is connected to the first input of the element KPI each of the computational block, the first bits of the first and second information output of the device, bits, except for the (i + 1) -th and (i + 2 / -th, output of the second of the computational block, the first bits of the first and second information output of the device, bits, except for the (i + 1) -th and (i + 2 / -th, output of the second device inputs are connected respectively to the first and second inputs of the EXCLUSIVE OR element, the output of which is connected to the second input of the AND element, the younger bit of the second information output of the device is connected to the (n + 1) th output of the second switch, connected to the second input of the OR element of each computing unit; the output of the second register of the last computing unit is the third information of the computational block, the first bits of the first and second information output of the device, bits, except for the (i + 1) -th and (i + 2 / -th, output of the second the first register of the i-th computing unit is connected to the corresponding bits of the information input of the second f register (+}) -th computing unit, (h + l) -and the output of the second switch of the m-th sixth unit is connected to the low-order bit of the information input the third register of the {i + 1) -th computing unit, and in the i -th computing unit you have the move of the second element is EXCLUSIVE OR connected to. (.p + 1) -th bit of the second information input of the third 91290299. ten the switch is connected to the first bit of the second register, the third control house of the output of the adder-subtractor, the second input of the second switch and the second swarm input of the OR element is connected to the control input of the first switch by a new input of the (2) th digit output element OR. five Tgg Editor M. Dshin Make up, drink A, Klyuev Tekhred L 0leynik Proofreader S. Cherni 7902/46 Circulation 673 Subscription VINILI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushskal nab. 4/5 Production and printing company, Uzhgorod, st. Project, 4 Tgg -T5G