SU786010A1 - Pulse repetition frequency with variable division factor - Google Patents

Description

one

The invention relates to a pulse technique and can be used in automation and computing.

A pulse frequency divider is known, which contains a pulse generator, a software block whose first output is connected to the input of a fractional coefficient decoder, and the remaining outputs to one of the digital comparator inputs, the other inputs of which are connected to the outputs of an integer coefficient counter, and the output to the first input switch

However, this device is not reliable enough to work with increasing frequency of the input signal.

The closest to the technical essence of the invention is a pulse frequency divider with a software task of a fractional division factor, comprising a pulse generator, a software block, the first output of which is connected to the input of the decoder of the fractional coefficient, and the other outputs to one of the digital comparator inputs, the other inputs which is connected to the outputs of the counter of the integer coefficient, and the output to the first input of the switch, phase shifting element, OR element, fractional coefficient counter, decipher frequency frequencies and target pulse extraction valves, the first inputs of which are connected via a phase-shifting element to the generator output — pulses, the second inputs — to the outputs of the frequency decoder, and the outputs — to the inputs of the OR element, whose output is connected to the counting input, to the counter of the integer coefficient and to the second input switch, the output of which is connected to the input zeroing

10 counter integer coefficient and one of the inputs of the counter fractional coefficient, the other input of which is connected to the output of the decoder fractional coefficient, and the output to the input of the frequency decoder, and the output of the digital comparator is connected

15 to the input of the program block

A disadvantage of this device is its low reliability with an increase in the input pulse frequency. The aim of the invention is to expand

20 operating frequency range while improving the reliability of the divider.

This goal is achieved by the fact that, in a pulse frequency divider containing a phase-shifting element, whose input is connected to the output of a pulse generator, a frequency switching unit, the first group of inputs of which is connected to the outputs of the phase-shifting element, the control input is connected to the decoder output, the input of which is connected to the output of the fractional part of the program block, and the integer coefficient counter, a shift register, an additional frequency switching block, the first group of inputs of which is combined with the first group of inputs, are entered in the frequency switch, the control input is from the control input of the frequency switch, and the output is connected to the first input of the shift register, the transfer unit, the match unit, the inverter, the trigger, the output of which is connected through the match element, the second input is connected to the output of the unit switching frequency, connected to the counting input of the counter of the integer coefficient, the entries of which records are connected to the outputs of the integer part of the program block through the transfer unit, and an additional decoder, the control input of which through the inverter is connected by the output of the frequency switching unit, the inputs of the bits are connected to the bits of the counter of the integer coefficient, and the output is connected to the second input of the register, the output of the first bit of which is connected to the first trigger input and the control input of the skew block, the output of the second bit - with the additional input of the frequency switching unit, the output of the rubbed bit - with the second trigger input, the output of the fourth bit - with the additional input of the additional frequency switching unit.

The drawing shows a structural electrical circuit of a pulse frequency divider with a variable time factor.

It contains a pulse generator 1, a phase-shifting element 2, a switching unit 3 often-, a fractional coefficient counter 4, a frequency switching unit, a fractionator frequency selector 5, a frequency switching unit AND -6, a frequency changer OR-7, an switching unit OR 7

frequencies, additional block on switching frequencies, program block 9, fractional coefficient decoder 10, transfer block 11, integer coefficient counter 12, additional decoder 13 of integer coefficient counter end state, shifting register 14, trigger 15, match element 16 inverter 17.

The device works as follows.

The pulses of the generator 1 are fed to the phase-shifting element. 2, where they are converted into FO, F, ... Fi, ... FiA pulses whose frequencies are equal to the frequency F of the pulse generator,

and the phases are shifted relative to each other by the value of D PJ, y

FO, Fi, ... Fi:, ... FM pulses are applied to the elements of block 3 and the additional block. The output of element 7 of block 3 passes only that sequence, which arrives at element 6, opened by the signal of the decoder 5, the state of which is set by counter 4. Counter 4 can operate in Mf 1 modes, each of which corresponds to its fractional fractional value and is set 10. For example, for the case of M 5, i.e. For the case of the scaling of the inputs of the phase-shifting element, there may be a variety of operating modes. In the first mode, the counter 4 is closed at the counting input and does not change its state. In this case, m 0, m is the fractional part of the division factor. In the second mode, +1, i.e. with the arrival of each counting pulse, the number in the counter increases by one, which corresponds to t 1/6. The third mode is + 2, i.e. with the arrival of each counting pulse, the counter content is increased by two, which corresponds to m 2/6, and so on to mode six, which can be formed as +5 or as - 1, i.e. either five is added to the contents of the counter, or the content is reduced by one, while rn.

The pulses from the element 7 of the block 3 are fed to the input of the element 16 and then to the counter 1 and through the inverter 17 are fed to the input of the additional decoder 13. Pulse; element 7 of the additional block 8 is fed to the input of the shift register 14. To the write inputs of the counter 12, block 1i receives the integer part code specified by the program block 9. The fractional part code of the division factor comes from the program block 9 to the decoder 10. Trigger 15 depending on state device allows or prohibits the passage of pulses to the counting input of the counter 12.

In the initial state, the shift register 4 is zeroed, the trigger 15 is set to the state allowing the counting pulses to pass through the block 16 to the counting input of the counter 12. The counter 12 records the number K equal to: DSC (H – E) mod (2.) - 3, where K is the number of bits in the counter;

e-specified division ratio (whole part);

It is the selected end state defined by the integer coefficient counter decryptor.

The counter 4 of the block 3 and the additional block 8 are set to the same state, i.e. the pulses at the counting input of the counter 12 and the shifting input of the shift register 14 go with the same phase.

After the counter 12 is set to the state determined by the additional decoder 13, the signal at the decoder output is only after the end of the counting pulse, through its pause, because the control input of the additional decoder is connected to the pulse bus arriving at the counting input of the counter through inverter. In this case, the recording “1 for the first bit of the shift register according to this clock cycle will not occur. The records "1 for the first bit of the shift register according to this cycle will not occur at the next counting pulse, since the phases of the pulses from the outputs of blocks 3 and 8 coincide. Progressing "1 on shifting reg 1page 14 causes the following switchings in the device.

The signal from the first bit of the shift register 14 switches the trigger 15 to the state prohibiting the passage of the counting pulses to the input of the counter 12 and enables the census of the whole part of the division factor from the software block 9 through the block 11 to the counter 12.

The signal from the second bit of the shift register 14 is fed to the counter 4 of block 3, which causes it to switch in accordance with the mode of operation specified by the program block 9 through the decoder 10, which determines the fractional part of the division factor.

The signal from the third bit of register 14 is fed to the input of trigger 15 and causes it to switch to the state allowing the passage of counting pulses to the input of counter 12.

The signal from the fourth bit of the shift register -14 is fed to the counting input of the counter 4 of the block 8 and translates it into the same state as the counter of the block 3, i.e. the signals supplied to the counting input of the counter 12 and the shift input of the register 14 coincide in phase.

In the future, the cycle of operation of the device is repeated.

The operation of software block 9 may be performed by commands given, for example, from the third bit of register 14 or by external commands.

Split device on. The two interconnected parts make it possible to divide the number of series-connected elements necessary for the operation of the device also into two parts, which makes it possible to reduce the minimum interval required for reliable operation, i.e. increase the maximum operating frequency.

Claims (1)

Invention Formula A variable division pulse frequency divider containing a phase-shifting element whose input is connected to the output of a pulse generator, a frequency switching unit, the first group of inputs of which is connected to the outputs of the phase-shifting element, the control input to the output of the decoder, the input of which is connected to the output of the fractional part software block, and an integer coefficient counter, characterized in that, in order to expand the range of working parts while improving reliability, shears are introduced into it conductive case, additional block switching frequency, a first group of inputs of which is combined with the first group of inputs of the switching of the frequency block control input - to the control the input of the frequency switch, and the output is connected to the first input of the shift register, the transfer unit, the coincidence element, the inverter, the trigger, the output of which through the match element, the second input of which is connected to the output of the frequency switching unit, is connected to the counting input of the integer factor counter, the write inputs through which the transfer unit is connected to the outputs of the whole part of the program block and an additional decoder, the control input of which is connected via an inverter to the output of the frequency switching unit, the bit inputs are from moves counter bits integer coefficients, and an output - to the second input shift register, a first bit output and which is connected to the first trigger input and the control input of the transfer unit, the output of the second bit with an additional input of the frequency switching unit, the output of the third bit with the second input of the trigger.