SU780174A1 - Digital sine-cosine converter - Google Patents

Description

The invention relates to automation and computer technology and can be used as a sensor for codes of sine-cosine dependencies · and pulses of large-angle angle marks 5 of the angle of rotation of the antenna in the primary processing of radar stations.

A digital sine-cosine converter is known, which contains a direct and inverted encoder sensor, the code switch and an adder, a memory unit, the address inputs of which are connected to the meter outputs 15, a synchronizer, the outputs of which are connected to the control unit, are connected to the corresponding outputs the high-order output of the direct and inverted code sensor is connected to the corresponding input 20 of the control unit, one of the outputs of which is connected to an additional input of the code switch, and the other two to the input s counter outputs the first group of the storage unit 25 soe- dinena with a first group of inputs and a multiplier output switch block codes, the second group of inputs of which is connected to the group output multiplier unit [1]. thirty

However, the known converter has insufficient speed.

The purpose of the invention is the increase in speed.

For this, an accumulating adder, two digital comparators, an OR-NOT element and a labeling unit are introduced into a well-known digital sine-cosine converter, · containing a direct and inverted code sensor, while the inputs of the OR-NOT element are connected to the second group of inputs of the multiplying block, with the inputs of the first code of the first digital comparator and the outputs K of the least significant bits of the code switch, the remaining outputs of which are connected to the inputs of the first code of the second comparator, the inputs of the second code of which are connected to the outputs meter and address inputs of the storage unit, the second group of outputs of which is connected to the inputs of the second code of the first digital comparator, the inputs of the term accumulating adder are connected to the outputs of the output code switch, the outputs of the first digital comparator, element. OR NOT and the additional outputs of the storage unit are connected to the corresponding inputs of the labeling unit, the outputs of the control unit are also connected to the additional inputs of the accumulating adder and the labeling unit, the output of the second digital comparator is connected to additional inputs of the output code switch and the control unit, respectively.

The drawing shows a structural electrical diagram of the proposed Converter. .

The converter contains a sensor of direct and inverted codes, a switch 2 codes, an adder 3, an accumulating adder 4, an output switch 5 codes, a multiplier unit 6, digital comparators 7 and 8, an element 15 OR NOT 9, a storage unit 10, a counter 11, a block 12 formation of marks, control unit 13 and synchronizer 14.

The converter operates as follows. 20

At the outputs of the first group memory unit .10 is generated six-digit code with the weight ratio of the angular LSB September ² · At the outputs of the second group of the memory unit 10 is produced, ny ³ shestirazryad- code angle 0 (LSB weight of this code is 2 February 31 ~ ^1g radian) one that complements the four-digit code on the address inputs of the storage unit 10 to the angle code, which corresponds to 30 ° mark 5 °. At the output 15 of the storage unit 10, a tag sign 5 °, (П ₁₅ 5 °) is generated, which corresponds to a combination of 0000 or 1000 codes on the address 35 inputs of the storage unit 10.

At the output 16 of the storage unit 10, a tag character 30 ° 'is generated (P. ₁ 30 °), which corresponds to com-! bination code 0000 on the address inputs of this block.

At the output 17 of block 10, the sign of the label 30 ° is produced taking into account the sign П ₁ 30 ° (P. ₁₇ 30 °) in such a way, if the four-digit code at the address inputs of the block .40 corresponds to the label ⁴ ° 30 °, then П ₁₇ 30 ° = 1, and if not, then П _Л7 30 ° = 0.

The control unit 13 contains three triggers and several logical combinational elements. ’Θ

The converter, using a 12-bit angle code 4, cyclically generates 10-bit codes sin phi cos 4, pulses of scale angle marks 5 '(M45 ^ and 30 ° (m 4 3 <f), and also generates a pulse of the end of determination sin 1 code and the pulse of the end of the definition of the cos cos code and gives this information to the outputs.

The high-order bits of the sίpal codes are cos 4 significant and are determined by the two high-order bits of the sensor 1. Therefore, the 12th bit of the sensor 1 is the sign digit of the code sin <<, and the sign digit of the code ssi is generated by adder 3 as the sum of the two logical values of the two highest discharges of the sensor 1.

Definition of codes of numbers | s! ηάI and I cos ФI is carried out by the method of piecewise linear approximation and the use of trigonometric reduction formulas.

The functions are approximated in an angle from zero to 90 °, which is divided into 16 equal sections, i.e. the calculation of the function Is (nil or I cosd-i is carried out according to the reduced angle p · or £, the 10-bit code of which is removed from the outputs of the switch 2 codes, where:

4 = 40 -! J B = 2JT2 ΣΣ2θ ·· Τ " P ⁿ D ^{willow enny} ANGLE whose magnitude is determined by the direct code 10 LSBs sensor 1,

the reduced angle, the value of which is determined by the inverse code of the 10 lower order bits of the sensor 1,

A. ··, 2 ^ '^ - respectively, the discharge and weight coefficients of the 1st discharge of the stroke of the sensor 1.

To convert the reduced angle to (e) is divided into two parts: 8- or - the control part, represented by the code of the four high-order bits of the switch 2 codes, ^or - the approximating part, represented by the code of the six least significant bits of the switch 2 codes.

Moreover, in the device using the control unit 13 codes 1 s i η <± | and | cos 41 are determined sequentially in each transformation cycle consisting of two periods T1 and T2. During the T1 period, the Isinil code is determined, and during the T2 period, the lcos F1 code.

For this, block 13, by the value of the 11th digit of sensor 1, generates * a control signal at the output for switch 2 of the codes in such a way that if a ₁ ^ = 0, then code B is removed from switch 2 during the period, and code during the period 8 and vice versa if a ^^ = 1.

Before the start of the conversion cycle, the adder 4 and counter 11 contain the results of the previous conversion cycle.

For definiteness, we assume that from this moment until the end of the conversion cycle under consideration, the code does not change, but a ^ = 0, i.e. before the start of the conversion cycle, the angle code 8 is removed from the outputs of the 2 code switch.

s

The conversion cycle begins when the start-pulse control unit 13 arrives from the synchronizer 14. According to this pulse, the block 13 generates the setting signal 0 of the adder 4 and the counter 11, and then generates a series of N1 pulses that are fed to the clock input of the adder 4 and the counting input counter 11.

, Moreover, N1 = j + 1, where:

. 4-7

1 = 1 — Jahi - the number of the ap * l section -> * · '···' of the approximation determined by the code Bj, aj can 'take values from the series 0.1 ,. . . , 15. ' ¹

Code B ₃ on comparator 8 is compared 15 with the current code B (t) of counter 11, which is received at the address inputs of block 10.

As a result of this, the comparator 8 generates a logic signal F _A = 0.20 if (t) and F = 1 if B: = 6 (t)! . ^{1 J}

The signal F _{a is} supplied to the control input of the output switch 2 codes and to one of the inputs of the control units 13.

Moreover, if F, = 0, then the inputs of the adder 4 are connected to the outputs of the first group of blocks 10, to which a six-digit code of the angular coefficient K _o , K _A , · .., K will be sequentially generated. Under

K _h is the code of the number (sin sin B,), the weight of the least significant bit of which is equal to '2' ⁹ . ,,

Since the converter is made on an elemental base, the triggers of which switch at the moment after the end of the pulses at their synchronizing (counting) inputs, after the end of the j-ro pulse of the N1 series, the adder 4 40 will contain the code number sin Bj, and the signal F _A will be equal to 1.

The signal F _A = 1, the switch 5 connects to the inputs of the term adder 4 the outputs of the multiplying unit 6. 45

The code β _αηηρ arrives at the first group of inputs of the multiplier block 6, and the code Kj

Therefore, the code of the number ed ^ αΐηηρ · K _d will be received at the inputs of the term of adder 4.

By Β _αηηρ in the expression Βα _ηηΡ 'Kj we mean the number between ”0 and 1, determined by the six least significant bits of code _B. After the end of the last pulse __ of the N1 series from the outputs of the adder .. 4, the code of the number S4v \ bj + + ⁶ apsh> · = '^ 4.1 will be taken.

Since when F _A = 1 Bj = e> (t), then at this moment the angle code ΐ> ₃ · arrives at the address inputs of block 10. 60

Therefore, for F _d = »1

- at the output 15 of block 10, the sign of the 5 ° mark (Π ^ δ ⁰ ) is generated, which corresponds to the combination V0000 or 1000 of the code 8 _δ ,. · 65

- at the output 16 · of block 10, the sign of the label 30 ° is generated (П ^ ЗО ⁰ ), which corresponds to the combination 0000 of the code 8-j

- at the output of block 17, 10 is produced with the P. _L. indication label 30 ° 30 ° (P ₇ 30 °), ^1b

- on the second group of outputs of block 10, the angle code _m ^ 'О is generated of such a value that complements the angle code to the angle code, which corresponds to the 5 ° mark.

The code is compared with the code θ _βηηρ comparator 7, the output of which produces a logical signal F _a = 0, if b _m * 8 _appr HF _a = 1, if ⁼ Β'αηηρ

The code in app _< > goes to the inputs of the element OR NOT 9 ,. the output of which produces a logical signal F _% = 1, if bspr = 0, and F. = 0, if Bq ^ _p 0. Logical signals n ^ j-5 ⁰ , П _1р 30 °, n _i7 30 °, F _x and F ₃ are supplied to the inputs of the label forming unit 12.

Since the code 6 is removed from the outputs of the code switch 2, the control unit 13 generates polling pulses by the signal F _A = 1 and the next clock pulse.

According to the polling pulse, which coincides with the last pulse of the N1 series, the marking unit generates 5 ° mark pulses (Md5 ⁰ ) if Π1δ5 ^β . F. VFX ·. = 1 and generates pulse mark 30 ° (M 4. 30 °),. if P., 30 * 4 * F _a VF _a · П ₁₇ 3 0 ° = 1.

After that, the control unit 12 connects the code δ to the inputs of the switch 2 of the codes and generates an end pulse of the conversion period T _A at the output of the device, according to which the sin <t code is removed from the device outputs.

On this period T ₁ consists and begins the period T ₄ , in which the control unit again generates the zero signal of the adder 4 and counter 11, and then generates a series of N2 pulses arriving at the clock input of the adder 4 and the counting input of the counter 11.

We take N _x = J + 1, _ islO where ^f e = ЕЗа. Y ' ⁷ - the number of the section approximation • (= 7''of the simulation, determined by the code 6j.

Since in the period T _{g the} calculation / cosd.) Is performed according to the reduced angle B, then the polling impulse 13 does not generate by the signal F _A ^w 1.

After the end of the last pulse of the N2 series, by the control signal from the control unit 13, the code switch 2 connects the corner code 6 to the outputs.

Then, the control unit 13 generates a conversion end pulse, according to which the code of the cosd number can be taken from the device outputs. At this point, the calculation cycle ends, and the next cycle starts only when the control unit 13 arrives from the synchronizer 14 of the next start pulse.

Thus, the pulses of the marks M45 ° and MdL30 ° will be generated by the last pulse of the N1 series, if a ^ = 0, or by the last pulse of the N2 series, if a.,., = 1, and the duration of the conversion cycle will be a constant value and is determined by the expression ^m = 1 _ty (a * M.

where is the period of the repetition rate of clock pulses of the synchronizer 14.

Therefore, in the general case, the duration of the transformation cycle time is _Λ ,,

Λ — О - К where η is the bit depth of sensor 1, the number of approximation sections, 25

K is the number of least significant bits of sensor 1, by which the function is approximated in the Jth section. jq

Claims (1)

780174 of the tagging unit; the outputs of the control unit are also connected to the additional accumulator inputs of the totalizer and the tagging unit, the output of the second digital comparator is connected to the additional inputs of the output code switch and the control unit, respectively. The drawing shows a structural electrical circuit of the proposed converter. The converter contains sensor 1 direct and inverted codes, switch 2 codes, adder 3, current adder 4, output switch 5 codes, multiplication unit b, digital comparators 7 and 8, element OR-HE 9, memory unit 10, counter 11, a tag formation unit 12, a control unit 13 and a synchronizer 1. The converter operates as follows. At the outputs of the first group of the storage unit .10, a six-bit code of the angular coefficient KJ is produced with a weight of the least significant bit 2. At the outputs of the second group of the storage unit 10, a six-bit code of the angle p &amp; O (the weight of the low-order series of this code is 2S radians), which supplements the four-digit code on the address inputs of the storage unit 10 to an angle code that is. rum matches the label. The output 15 of the storage unit 10 generates a sign of the 5 ° mark, (p. 5) which corresponds to a combination of 0000 or 1000 code on the address inputs of the storage unit 10. The output 16 of the storage unit 10 produces the sign of the 30® mark (P., 30 °) which corresponds to the combination of the 0000 code on the address inputs of this block. At output 17, unit 10 is produced taking into account the sign П ,, 30 ° recognizing 30 ° marks (P., 30 °) thus, if the four-digit code at the address inputs of the block .0 corresponds to mark 30, then П, ЗО 1, and if not, then P 30 ° 0. BLO.K 13 controls contains three trigger and several logical combinational elements. A converter of 12 bits of the angle d code code cyclically generates 10 bit sinolH cosdl codes of the .SCMitSTi scale angle tags and 30 ° (MA3Cf), and also generates a sin A code end pulse and a cos code end pulse. dC and gives this information to the outputs. . The upper bits of the cosip smart cosi codes are sign and determined by the two major bits of sensor 1. Therefore, the 12th digit of sensor 1 is the significant code bit, and the significant bit of the cosA code is generated by the adder 3 as the sum of two parameters. the two most significant bits of the sensor 1. The determination of the codes of numbers (and / сsd.1) is carried out by the piece-linear approximation method and the use of trigonometric coercion formulas. The functions are approximated at an angle from zero to 90 °, which is divided into 16 equal sections, i.e. fun 151pl | or 1coc5 is produced at a reduced angle P or, a 10-bit code of which is removed from the outputs of the switch 2 codes, where:. a reduced angle whose value is determined directly by the code of the 10-least significant bits of the sensor a 1, . ,, -) “..,. TIa-- is the reduced angle, the value of which is determined by the inverse code of the 10-least bits of sensor 1,, 2 are, respectively, the bit and weight coefficients of the 1st bit of sensor 1 stroke. For conversion, the reduced angle ft (V) is divided into two parts: fcj or 6 - the control part, represented by the code of the four most significant bits of the switch 2 codes, appr and "cnr - the approximating part, represented by the code of the six least significant bits of the switch 2 codes. In this case, in the device using the control unit 13, the Isindl and ICOSAI codes are determined sequentially in the X1 every conversion cycle consisting of two periods T1 and T2. during the period T1, the code Isinil is determined, and during the period T2, the code Icos ctl. For this, block 13, by value 11 - GOD of sensor 1, generates a control signal at the output for switch 2 of the codes so that if aO, then during the period T from the switch 2 the code B is removed, and during the period T the code B and vice versa, if a 1. Before the start of the conversion cycle, the adder 4 and the counter 11 contain the results of the previous conversion cycle. For definiteness, we will assume that starting from this point until the end of the transformation cycle in question, the code does not change, but O, i.e. Before the start of the conversion cycle, from the switch output 2 codes, the angle code b is removed. The conversion cycle starts with the arrival of the synchronizer 14 to the start-impulse control unit 13. At this impulse, the DZ unit generates a setting signal in O of the adder 4 and counter 11, and then generates a series of N1 pulses that arrive at the clock input of the adder 4 and the counting input of the counter 11. Moreover, N1 j + 1, where:, is the part number of the ap1x7 proximization, defined by the code Bj, and j may take values from a row of 0.1, ...., ...., 15. The cd 8.J on the comparator 8 is compared with the current code in (t) of the counter 11 arriving at the address inputs of block 10. As a result, the comparator 8 generates a logical signal F if (t) and F 1 if b: in (t) . The signal F is fed to the control input of the output switch 2 of codes and to one of the inputs of the control units 13. In this case, if F 0, then the inputs of the addendum adder 4 are connected to the outputs of the first group of blocks 10, to which the six-digit code of the slope coefficient Kc, K, will be sequentially generated. .., K, ..., K. By K is meant a code of a number (sin 6 + S i p)), the weight of which of the lower order is equal. Since the converter is made on the element base, the trigger of which is switched at the moment after the end. If there are no pulses on their sync (counting) inputs, then after the end of the j-ro pulse of the N1 series, the adder 4 will contain the code of the number si n Bj, and the sign F will be 1. By the signal G 1 KONwyraTop 5 connects the sum of the torus 4 to the inputs of the summand outputs of the multiplying block 6. The first group of inputs of the multiplying block 6 receives the Idppr code to the inputs of the second - the code. Therefore, the code of the number oinnp 3 will be received at the inputs of the sum of torus 4. Under the OPPR of the expression 6o, nn "- K-j, the number between O and 1 is defined, defined by the six least significant bits of code 8. After the end of the last pulse of the N1 series. From the outputs of the adder 4 will be removed the code number .j + bc, n „.- K.) g ,, ,,,. Since for F 1 b e (t), then at this moment the block 10 receives the code of the angle bj at the address inputs. Therefore, when F i - output 15 of block 10 produces the sign of tag 5 (), which corresponds to the combination 0000 or 1000 of code 6, -the output 16 of block 10 produces the sign of mark 30 (),; to which the combination 0000 corresponds to the code BJ, -the output 17 of block 10 is produced by considering P., a 30 ° mark of a 30 ° mark (P ,, 30). - in the second group of outputs of block 10, an angle code is generated. About such a value that complements the angle code B, up to the angle code to which the 5® mark corresponds. The codeB is compared with the code of the comparator 7, at the output of which a logical signal Fa is generated. Oh, if b, and F, j 1, if - “nod CodeVappr arrives at the inputs of the element OR NOT HE 9 ,. at the output of which a logical signal F 1 is generated, if l Opp, and Fj O, if VOSHPR O.. Logic signals, P 30, 30 °, F and FJ are fed to the inputs of the tag formation unit 12. Since code 6 is removed from the outputs of switch 2, the control unit 13 generates polling pulses from the signal F 1 and the next clock pulse. By a polling pulse matching the last pulse of the N1 series, the tagging unit 12 generates 5 (MdS) mark pulses, if 5 °. FI VFj. 1 and produces 30 ° (Md, 30) mark pulses,. if P.,) jV F, - 30 ° 1 After that, control unit 12 connects code B to the switch inputs 2 and generates a pulse at the device output at the end of the conversion period T, which is used to output the code slnd at the output of the device. At this period T the period T, is concluded and begins, in which the control unit 13 again generates a signal for setting zero of the adder 4 and the counter 11, and then produces a series of N2 pulses arriving at the clock input of the adder 4 and the counter input of the counter 11. Let us accept NJ + 1,. where .2 is the plot number approximation) of 7 simulations, defined by the code Bj. Since in the period T the calculation / cosd) is performed on the reduced angle B, then by the signal F 1 the control unit 13 does not generate a polling pulse. After the end of the last N2 series pulse on the control signal from control unit 13, switch 2 codes connects the angle code B to the outputs. Then control block 13 generates a conversion end pulse, which can be used to remove the code of the cosd number from the device outputs. and the next cycle will start only with arrival to the control block 13 from the synchronizer 14 of the next start-pulse. Thus, MdS and MdLSO pulses will be generated by the last N1 series pulse, if a is O, or by the last N2 series pulse, if a 1, and the conversion cycle time is constant and is defined by the expression (), where t- ., is the period of the clock pulse frequency of the synchronizer 14. Therefore, in the general case, the duration of the conversion cycle time is the sensor 1, the number of approximation areas, the number of the low-order digit 1, by which the function is approximated by JM plot. The invention includes a digital sine-cosine transducer containing a direct and inverted-encoder, the corresponding outputs of which are connected to a code mutator and an adder / storage unit whose address inputs are connected to the outputs of the counter, synchronization, and the outputs that are connected to the Control unit , the output of the higher row sensor of the forward and inverted codes is connected to the corresponding input of the control unit, one of the outputs of which is connected to the auxiliary input of the switchboard codes, and the other two to the counter inputs, the first group of outputs of the storage unit is connected to the first group of inputs of the multiplying unit and the output code switch, the second group of inputs of which is connected to the group of outputs of the multiplying unit, so that, in order to increase speed, the accumulating adder, two digital comparators, an OR-NOT element and a tag formation unit are entered, and the inputs of the OR-NOT element are connected to the second group of inputs of the duplication block, to the inputs of the first code of the first digital comparator and from the output and To the lower bits of the switch codes, the remaining outputs of which are connected to the inputs of the first code of the second comparator, the inputs of the second code of which are connected to the outputs of the counter and the address inputs of the storage unit, the second group of outputs of which are connected to the inputs of the second code of the first digital comparator, the inputs of the addendum accumulating adder connected to the outputs of the output switch codes, the outputs of the first digital comparator of the element OR NOT and additional outputs of the storage unit connected to the corresponding inputs labels forming unit, the control unit outputs are also connected with additional input of the accumulator and labels forming unit, an output of the second digital comparator is connected to additional inputs respectively output codes and switch control unit. Sources of information taken into account in the examination 1. USSR author's certificate in accordance with application 2440317, class H 03 K 5/156, 1977.