SU1188669A2 - Digital phasemeter - Google Patents

Abstract

DIGITAL PHASOMETER St. No. 1045155, characterized in that, in order to expand the functionality by providing and measuring the frequency, the input signal, a second code encoder and a synchronizer are inputted to it, the control input of the second code encoder is connected to the first synchronizer input and to the sixth output of the control unit The outputs of the encoder of the second code are connected to the inputs of the combining unit, which is equipped with the third group of inputs; the second and third inputs of the synchronizer are connected respectively to the fifth and seventh outputs of the control unit, Werth synchronizer input connected to the output of the adder sign bit, a first synchronizer output is coupled to a fourth input of the control unit, the second and third synchronizer outputs connected respectively to first and second inputs of D (shear giste A fourth synchronizer output coupled to an input of the second shift register.

Description

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The invention relates to a measurement technique, can be used both for measuring phase shifts, and the frequency of the signals under study with high measurement accuracy and device speed and is complementary to the author. No. 1045155.

The purpose of the invention is to expand the functionality.

This is achieved by highly accurate determination of the signal frequency over one measured period by comparing the measured period of the signal with the selected time measure in the form of a code of the number N corresponding to a second.

The drawing shows a block diagram of the proposed device.

The digital phase meter consists of a driver 1, the first and second inputs of which are connected respectively to the first and second input buses of the device, control unit 2, first electronic switch 3, first pulse counter 4, first valve block 5, combining unit 6, register 7, adder 8, the second valve block 9, the second electronic key 10, the second pulse counter 11 of the first shift register 12, the second shift register 13, the registration block 14, the pulse generator 15, the encoder 16 of the second code, the synchronizer 17,

In addition, the synchronizer 17 consists of the key 18, the driver 19 of the shift signals to the right, the driver 20 shift to the left, the reversible counter 21 pulses, decoder 22, the first circuit OR 23 and the second circuit OR 24.

In this case, the inputs of the phase meter are connected via the driver 1 to the input of the control unit. The generator 15 is connected to the input of the synchronizer 17 and through a series-connected key 10, counter 11, shift register 12 to the second group of inputs of the adder 8, as well as through key 3, counter 4, valve block 5, combining block 6, register 7 to the first group of inputs the same adder 8. The control unit 2 is connected to the outputs of the second inputs of keys 3 and 10, the valve block 5, the encoder 16 of the second code, the block of 9 veils, the synchronizer 17 and its inputs connected to the first and second outputs of the synchronizer. The sign register of the adder 8 is connected to the input of the shift register 13 and the first output of the synchronizer 17, the third output of which is connected to the second input of the shift register 13 connected by the outputs to the registration unit 14. The fourth and fifth outputs of the synchronizer are connected respectively to the control inputs of the register 12. The information outputs of the adder 8 through the valve block 8 are connected to the third inputs of the combining unit 6, the second inputs of which are connected to the information outputs of the encoder 16 of the second code.

The device measures (in one period) the phase shift (fx between two sinusoidal signals or the frequency F of one of them depending on the position of the key 18 and operates as follows.

The inputs of the imaging unit 1 receive sinusoidal signals U and Uj with a frequency F. The imaging unit 1 converts the input sinusoidal signals into square impulses, the leading edge of which coincides with zero crossings of the input voltages. These pulses enter the input of the control unit 2, which simultaneously forms two rectangular impulse having a duration of Cf and Cf. The pulse duration is proportional to the phase shift between the input signals. The duration is equal to the period of the investigated voltage T (T 1 / F). Using the generator 15 pulses and electronic keys 3 and 10 pulse duration, and c. converted to timed N codes, respectively. The code is fixed in a 4-pulse counter and is not used in frequency measurement. The code N is recorded in the pulse counter 11. Wherein

N 1Y,

where 6 l / f .. „is the frequency period kw

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Measurement of the frequency of the voltage under investigation using the proposed device (for one period) is based on determining the number of integer periods of the voltage under study and its fractional parts, which fit in the time base equal to 1 s. In this case, instead of the actual time base 1 s, its numerical equivalent N is used. The value N is determined by the value of the frequency of the generator 15 pulses N KB-c. This number N in the proposed device is formed in the forward binary code using an encoder of the 16 second code. The process of determining the frequency of the signal F under investigation in the proposed device consists of three stages: determining the number of binary bits n needed to represent the integer part of the measured frequency value; forming the t-bit binary code of the measured frequency (t is the number of binary bits of the digital part of this device; fixing the comma between the integer and fractional parts of the measured frequency code; the current number n of binary bits needed to represent the integer part of the measured frequency, c with the help of the inequality n4-1 Sogj- d) which is equivalent to the joint implementation of inequalities. The solution of these inequalities is carried out by successively multiplying the number N by 2, comparing these products with the number N, counting and fixing the numbers and n these comparisons. This operation in the proposed device is carried out as follows. From the pulse counter 11, the code N is written to the shift register 12 and is fed to the inputs of the adder 8, which has m binary bits, not considered significant. The binary code of the second N is read from the encoder 16 of the code of the second, written into register 7 and fed to the second inputs of the summator b. In the latter, the difference N - NT is formed, the sign of which fixes with in the sign bit of de adder 8. If the current difference N is N - ,. 0, then the synchronizer 17 generates a shift control signal one bit to the left (towards the higher bits) the contents of the register 12 shift. At the same time, the NT code is shifted one digit to the left, which is equivalent to multiplying the number N by 2, and one pulse is received in the reversible counter 21 pulses, which works on addition. After this, the second difference N-2 N is formed in the adder 8. is positive, then the contents of the shift register 12 are shifted by the bit to the left, and a second pulse enters the reversible pulse counter 21. If adder 8 fixed the nth difference with a negative sign, then the contents of motor register 22 equal to 2 Nf are no longer shifted to the left, and the binary code of number n is fixed in the reversible counter 21 pulses. Thus, the reduced system of two inequalities is solved and The number of bits n needed to represent the integer part of the measured frequency value in this measurement was determined. At this point, the first stage of operation of the device ends. Note that the value of n can be O, 1, 2, ..., TV depending on the value of N. In the second stage, the device determines in digital form which integer number of periods T and which fractional part of it is placed in the time base, equal to t with. At the same time it forms the corresponding binary code frequency. To determine the digit digits (where Of, is ravof,, ", but O or t) of this code, this device sequentially generates w differences: N - 2 Nf (), a,, ..., - - -. a;, ..., a „.- N« ““, a, m- “quantity, identical to the sign of the current aj difference, i.e. if aj Otov / J 1, otherwise OS J 0. Note that IR, is the first significant digit of the measured frequency code. The weight of this unit is 2. From the above expressions for the difference in a, it follows that when of, (aj (О)) the value 2 N is used to determine the difference .. Otherwise, the previous difference can be used to write the difference, the expression N- NvU (x, ... +. ,, + 2Vn + .2-V ",, t.,.) T2- N. From the last expression it follows, then with an error of ± 2 N.-, tending to zero with increasing the numbers t, in the numerical equivalent of the time base 1 s, fit 2 +, ..., + 2 integer numerical equivalents of the period and its fractional value

part + ... + 21. Wherein

about h +1 ifi

the sum of the terms on the right side of the above expression is the numerical value of the measured frequency code. If we successively memorize the value of W, using the shift register, then, after determining the sign of the mth difference, the parallel binary code of the measured frequency value is fixed in the shift register.

The proposed device performs the described operations as follows. After the first shift in the shift register 12 in the adder 8, the positive difference aj N - 2 N 0 is always formed. The sign of the first difference 1 is formed in the sign bit of the adder 8 and is written to the first (younger) bit of the shift register 13. At the same time, the current difference value is written to register 7. After that, a second shift of the contents of the shift register 12 is made, and the second difference is formed in the adder 8 and N If the second difference is positive, then one (t) is written to the lower digit of the shift register 13 , In this case, the unit recorded in the previous cycle (o ;, 1) is shifted by bit to the left (towards the higher bits), and the code of the second difference, a, is written to register 7. If the difference is negative, 7, then the least significant bit d shift register 13 is written zero (0), and in reg Streit 7 remains npe) SHee difference value, i.e.

difference a. In the remaining t-2 cycles, the device operates in a similar way. . After conducting m cycles, shift register 13 fixes the t-bit binary code, the digits of the wasps, which are significant digits of the frequency of the signal under study.

Consider the third stage of the device. In this device, the symbolic comma separating the integer and fractional parts of the result of the measured frequency is tied to the j bits of the shift register 13. This is provided by shifting the contents of the shift register 13 by n bits to the left. After that, the fractional part of the measurement result will always be located in the low-order bits, and the entire part in the high-order bits of the shift register 13 is intact. If is the maximum value of the measured frequency, then to place its integer part, it is necessary to have binary bits. The value of p d is determined by the ratio

Fri x

Thus, the shift register 13 must have m + n "d binary bits. The code shift of the measured frequency value is performed as follows. When a shift pulse is applied to the shift register 13, its contents are successively shifted to the left. At the same time, the value of the code n, recorded in the reversible counter of 2 pulses, decreases successively by one. At the third stage, this counter works on pulse subtraction. The shift of the contents of the shift register 13 is performed until the current content of the reversible pulse counter 21 is equal to zero.

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Claims (1)

DIGITAL PHASOMETER by ed. St. No. 1045155, they distinguish me by the fact that, in order to expand their functionality by providing and measuring the frequency .. of the input signal, a second code encoder and synchronizer are introduced into it, and the second code encoder control input is connected to the first synchronizer input and the sixth output of the control unit, the output of the code encoder second is connected to the inputs of the combining unit, which is equipped with a third group of inputs; the second and third inputs of the synchronizer are connected respectively to the fifth and seventh outputs of the control unit, fourth synchronizer input connected to the output of the sign digit of the adder, a first synchronizer output is connected to fourth input of the control unit, the second and third synchronizer output connected respectively to the inputs of the first and second shift registers, fourth synchronizer output is connected to the input of the second shift register.