SU767750A1 - Binary-to-binary-decimal code converter - Google Patents

Description

The invention relates to the field of automation and computer technology and can be used in the construction of binary-decimal converters. . Known converter of binary code into binary-decimal code of degrees, minutes and seconds, containing input register, pulse generator, binary counter, AND element, decoders, AND block, OR block and binary decimal group l The disadvantage of the known converter is in its relatively low speed. The closest solution to the invention is by technical essence, and the circuit solution is a binary code converter into a binary-decimal scaled code containing an input register, the information inputs of which are connected to the converter inputs. In binary-decimal counters, where Mind is the number of tetrads of the output code. YY of the elements OR, (YN-1) of the delay elements, pulse distributor, pulse generator, element I, the first input of which is connected to the output of the pulse generator, and the output - with the clock input of the pulse distributor, A1 groups of elements AND, the first inputs of which are connected to the outputs the input register, the second inputs - with a group of outputs of the pulse distributor, and the outputs of the elements AND of the group - with the inputs of the corresponding elements OR; the output of the Lth (l 1-Mi) element OR is connected with the counting input 4 of a binary-decimal counter, the overflow output of which through the -i-and the delay element is connected to the input (i + l) -ro of the OR element. In addition, this converter contains an equivalent encoder and a decimal counter 12. The shortage of this converter lies in its relatively slow speed. The aim of the invention is to increase speed.

The goal is achieved due to the fact that the binary code-to-binary scale converter is converted to a binary code. A biased code containing an input register whose information inputs are connected to the converter inputs, CUs of binary-decimal counters, where W is the number of tetrads of the output code, Vvi elements OR, (Vvi-1) delay elements, pulse distributor, pulse generator, and element the first input of which is connected to the output of the pulse generator, and the output to the clock input of the pulse distributor, Wi groups of elements I, the first inputs of which are connected to the outputs of the input register, the second inputs to the group, the outputs of the pulse distributor, and The outputs of the AND elements of the group are with the inputs of the corresponding OR elements, the output of the 1st (1 1-element OR is connected to the counting input of the lth binary-dbs counter meter, the overflow output of which through the 1-th delay element is connected to the input ( 1 + 1) of the OR element, the control trigger and Vv of additional groups of elements AND whose first codes are connected to the first output of the pulse distributor, the second inputs to the corresponding outputs of the input register, and the outputs of the elements of the additional groups are additionally connected to the input inputs I give the corresponding binary-decimal counter. The second output of the pulse distributor is connected to the input input-register zero input and the control trigger input zero, the unit output of which is connected to the second input element I, the control trigger input - to the pulse distributor start input and the control input of the converter, recording input the input register and the reset inputs of binary relative meters. . FIG. 1 shows the flow chart of the proposed converter; on . FIG. 2,. oh and fig. 3, a, b are presented -time diagrams that explain his work.

The converter contains an input register 1, inputs connected to the inputs of the converter, a generator of 2 pulses connected to the first; input element I 3, to the second input of which the control trigger 4 is connected. Single; trigger 4 control of the connection with the BKOjfOM distributor 5 tpugpulsov, in the house of the record of the input register 1, and neg-677504

The output input of the trigger 4 control is connected to the input of the input register 1 and the output of the distributor 5 pulses, the group of outputs of which is connected to the first

5 inputs of the MP groups of elements And 6, the second inputs of which are connected to the corresponding bits of the input register 1. The outputs of the groups of elements AND 6 are connected to the first inputs of the pvi elements OR

(About 7, which outputs are connected to the inputs Wi of binary-decimal counters 8, and the second inputs - to the outputs (AT-1) of delay elements 9 in all tetrads, except the youngest; yy, the second groups of elements 5 toy and 10 the first inputs are connected to the corresponding bits of the input register 1, the second inputs to the output of the distributor 5 pulses, and the outputs to the installation inputs ui of binary 20 decimal counters 8. The single input of control trigger 4 is also connected to the reset input of binary decimal counters and controlling the input of the converter ..25 The Converter operates as follows.

The signal at the control input of the converter (see Fig. 1 and Fig. 2, a)

30 information from the information inputs is recorded in the input register 1. With the same signal, the binary-decimal counters 8 and the distributor 5 pulses are reset, set to one.

trigger 4 controls (see Fig. 2, o),. which permits the passage of pulses for a generator of 2 clock pulses (see FIG. 2.6) through the element I 3

40 (see Fig. 2, c) to the distributor 5 named after pulse E1.

Further, the operation of the converter is carried out in two stages. During the first

From the first output of the distributor 45 5 pulses, a single pulse is emitted, by means of which codes corresponding to certain bits of input register 1 are recorded (matching of codes with bits of input register JQ of par 1 will be explained by examples 1 and 2) 10 in hi: binary-decimal counters 8 (codes that do not require transfer signals when summing, for example: 0101 + 0010, ITO + O01, etc.). - Thus, a part of the information from the binary code on the input register 1 is transformed. B binary-decimal scaled code to be converted

numbers This completes the first conversion conversion.

During the second stage, from the distributor of 5 pulses, the first inputs Wi of groups of elements I 6 receive the formed packets of 1,2,3. . .or 9 pulses (see fig. 2, m-d). Information from the corresponding bits of the input register 1 arrives at the second inputs of the control codes of the groups of elements And 6 (the correspondence of the bits of the input register 1 to certain packets will be explained with examples 1 and 2). Depending on which of the input bits, register 1 are in unit distance, one or another group 6 elements and the corresponding packets (-CM. Fig. 2, d-i) are triggered through the elements OR 7 to the counting inputs of Ui of binary-decimal counters 8, summed with the information recorded in wi of binary number counters as a result of the first conversion step.

If, as a result of reading the next packet, the pulses in the second conversion step arise, the transfer signals are sent to the next counter, then the transfer signal is delayed by the correct counting of pulses in the next tetrad. one of the (Vvbl) delay elements 9 in this way (see Fig. 3.6) so that it fits between the pulses; (see Fig. 3, a). Upon completion of the cycle, the second output of the pulse distributor 5 receives a pulse, which sets the control trigger 4 to the zero state and the input register 1 stops thus the operation of the converter. This completes the second stage of the conversion. - -. .

In one cycle of the distributor 5 pulses, as a result of two stages of conversion in binary codes of binary-decimal counters 8, the required binary-decimal code is generated, which is fed to the output trunks of the converter. With the next impulse, the start of the conversion sets all Vn of the binary-decimal counters 8 to the initial state, the distributor 5 pulses, a new binary number is written to the input register 1, the control trigger 4 is set to one and the cycle repeats.

The cycle time of the distributor 5 pulses determines the speed

converter, which can be determined by the following formula: ..

4-V (.q, VQ, P2 -... and where t pp is the conversion time;

the first term is the duration of the first stage of the transformation, the second term is the duration of the second stage of the transformation;

t | - is the duration of the pulse clock period; Q-i - the number of packets containing j - pulses; p- is a packet of j pulses arriving at one of the outputs of the distributor 5 pulses;

j - 1,2 ... 9.

The accuracy of the conversion is determined by the resolution (AND) of the input binary. the code and the number of binary-decimal counters (Ul) taking into account (lifVY -and).

Example 1. Table 1 shows the correspondence of the bits of the input register to 1 codes recorded in Vvi by binary partition counters through the UP of groups of elements I 1O, as a result of the first stage of conversion (codes are underlined) and through U1 of groups of elements of And b - as a result of the second stage, conversions (unstretched codes) For the slant H - “- 100, AND - 15, 4, where Is the tenth number into which the binary code is converted; and - binary code size; - number of output code tetrads; B- is the weight of the corresponding i-th bit of a binary code, defined by the following expression:. On

D- oh-l

iCi) -2,

where Vi is the number of binary bits; -t-n -and binary bit at (1.2..... And), where is the highest bit; Vl is the low-order bit, B, and the weight of the decimal number N corresponding to 1 binary bit is determined by the following expression. Niem: -L.

i (10) 2i

Br is the representation of the tetrad code in the decimal number system; B, ..- representation of the tetrade code in binary number system. The coefficients a are determined from Table 1 as follows. .

First, from the table. 1, the values that are converted to binary are selected, the code of the number N as a result of the first stage of the conversion, i.e. direct entry on the Mind binary 7 7677598

decimal counters 8 through ele-i groups (for example, in the fourth tetrad two

cops and 10. These are codes that do not require a float), then the coefficient a "to

transfers at summation (in Table. 1 (a C). If none of the columns

they are underlined.) (10) ® FR-Equal; j, then a ", 0 (nor

Then, from the values, without getting ;;: in one of the columns there are no fours,

The second stage is determined by the coefficient. e. and O).

al for the second stage of the conversion. From the example given (see Table 1

If the cat would be in the same post. , and FIG. 2, dm) we get a «1; a s: 1;

corresponding to a specific tetrad, a, a 1; but. - ABOUT; ag and 2; a / o; a- si;

there are k - identical numbers equal to about 1; and ““ 1.

I. .Table

Thus, from the above, the measure follows that the pulse distributor should generate the following signals: one pulse for the first conversion step (see, Fig. 2, d); pulse packets for the second stage of conversion in composition (see Fig. 2, dm); by

one impulse - 1 packet, two each, one, three - 1, five, two - two, seven -1, eight - 1, nine-t1.

Example 2. In table. 2 shows the correspondence of the bits of the input register to the 1 binary-decimal code of the number N 6.2832 (2U; s16) S 5.

The coefficients a for example 2 are as follows: a2, "2; a, 2; U-2; .

The use of the invention in comparison with existing gives the following; Advantages: the ability to display measured parameters in various units of measurement (for example, in%, degrees, radians, in natural units, etc.); to obtain sufficient speed of the converter at a low cost of equipment.

The conversion time of the claimed converter for example 1 (N-100, VI s: 13, μs) is tj ,, l + 1 (1.1 + 1.2 + 1.3 + + 0.4 + 2.5 + 0, 6, + 1.7 + 1. 8 + 1.9); 42 ISS.

The conversion time of converter 2 is determined by the formula

tnp-09 -bf.-Vl: qHH: 5: l-17N KC.

Thus, it can be seen that the speed of the claimed device is higher than that of the known, by 2.8 times,

Ф о рм ул а and 3 о б ретини

A binary code converter into a binary-decimal scaled code containing an input register, the informational inputs of which are connected to the converter inputs, ki binary part-time counter, where kz is the number of output code tetrads, hi elements .OR, (Vfl-l) elements delays, pulse distributor, pulse generator, And element, the first input of which is connected to the output of the pulse generator, and the output - with the clock input of the pulse distributor, PA of the groups of elements And,. the first inputs of which are connected to the outputs of the input register, the second inputs are with a group of outputs of the pulse distributor, and the outputs of the elements AND groups / py are connected to the inputs of the corresponding elements OR, the output -i () of the element OR is connected to the counting input of the 4th binary - a local counter, the overflow output of which is connected via the i -th element

with the input of the (4 + 1) th OR element, characterized in that, in order to increase speed, a control trigger and additional groups of AND elements are introduced into it, the first inputs of which are connected to the first output of the pulse distributor, the second inputs are connected to the corresponding outputs . the inputs of the input register, and the outputs of the 10 elements And additional groups are connected to the installation inputs of the corresponding binary-decimal counters, the second output of the pulse distributor is connected to the input of the installation 3 to the zero of the input register and to the input of the installation to zero of the control trigger, the single output of which is connected to the second the input element And, a single input of the control trigger is connected to the 0 input of the start of the pulse distributor and the control input of the converter.; ..

Sources of information,: taken into account in the examination of 5-1. USSR author's certificate No. 521-564, cl. Q 06 F, 5/02, 1976 .:

2. USSR author's certificate N 641441, cl. Q 06 F 5/02, 1976 (prototype). .

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Claims (1)

Claim The converter of the binary code to binary decimal scaled code containing the input register, inform. the mation inputs of which are connected to the inputs of the converter, Ш a double-decimal counter, where y is the number of tetrads of the output code, Wi OR elements, (УЦ-1) delay elements, a pulse distributor, a pulse generator, an AND element, the first input of which is connected to the output of the pulse generator, and the output - with the clock input of the pulse distributor, the mind of the groups of AND elements, the first inputs of which are connected to the outputs of the input register, the second inputs - with the group of outputs of the pulse distributor, and the outputs of the elements AND groups are connected to the inputs, respectively of existing OR elements, the output of the -th (ί l.: 1-Ρΐ) OR element is connected to the counting input of the 4th binary decimal counter, the overflow output of which through the 4th delay element is connected to the input (4 +1) —th OR element, characterized in that, in order to increase performance, a control trigger and the mind of additional groups of AND elements are introduced into it, the first inputs of which are connected to the first output of the pulse distributor, the second inputs are connected to the corresponding outputs of the input register, and outputs of elements AND additional groups connected s with the setting inputs of the corresponding binary decimal counters, the second output of the pulse distributor is connected to the input of the zero setting of the input register and to the input of the zero setting of the control trigger, the single output of which is connected to the second input of the AND element, the single input of the control trigger is connected to the trigger input of the distributor pulses and the control input of the converter.