SU760425A1 - Device for discriminating the first and the last pulses in pulse train - Google Patents

Description

The invention relates to the field of pulse technology and can be used in information processing devices.

Known time interval meter [DZ, in which the selection of the first and last pulses in a pack, containing a pulse counter, a coincidence circuit, a counting trigger, a driver, a last pulse extraction circuit, a memory device, two anti-coincidence schemes and corresponding connections.

A disadvantage of the known device is the structural complexity and the fact that the selection of the first and last pulses is not in each pack, but after one, and the number of pulses in each packet arriving at the input of the known device 20 must be the same, otherwise it cannot function. All this limits the scope of the device.

25

The closest to the invention

technical entity is a device | 2 ^ containing two triggers,

two elements And, pulse counter, _

coincidence circuit, counting trigger, 30

shaper and related connections.

The known device also has all the disadvantages of the first analogue, i.e. it is structurally difficult and has a narrow scope.

In a known device, a relatively large amount of equipment is used. The most complex node is a reversible counter, in which the number of series-connected counting triggers depends on the maximum possible number of pulses in a burst.

The narrow scope of the known device due to a number of 'reasons. Firstly, it cannot function normally if pulses are received at its input, the number of which in the packet exceeds the counting counter (for example, a number greater than 63 cannot be entered into a six-meter counter). Secondly, it allocates the first and last pulses not in each pack, but through one, since the first packet of pulses is used to prepare the circuit, and from the second pack it produces the selection of pulses. Thirdly, the number of pulses in each pack, by 760425

given to the input of the known device must be the same, otherwise it does not function. In some cases, for example, when scanning a discrete raster in alphanumeric displays, the number of pulses in each burst may be unequal and the input of the first and last pulses must be in each burst without gaps.

The purpose of the invention is to simplify the device and expand its scope.

This goal is achieved by the fact that in the known device, which contains three elements AND-NOT and the trigger, the inputs of which are connected to the outputs of the first. first and second cements AND- ^ NOT, a delay node, two inverters and a fourth AND-NOT element are entered, the first input of the first AND-NOT element is connected to the Output of the first inverter and the first input of the delay node, the second input of which is connected to the first input of the device, and the output with the second input of the first NAND element and the first input of the third NAND element, the second input of which is connected to the second input of the device and the input of the first inverter, and the output through the second inverter is connected to the first input of the second NAND element, the second input which is connected to the 'out Do a fourth AND-NO element, whose first input is connected to the output latch, the second - with output of the second AND-NO element.

The drawing shows a functional diagram of the device.

The device contains a node 1 delay, inverters 2, 3, elements AND NOT 4-7, trigger 8, bus. 9 bursts of pulses, the bus 10 synchronizing pulses, the output bus 11 of the first pulse of the pack, the output bus 12 of the last pulse of the pack, the bus 13 of the inverse of the packs of pulses, the bus 14 of the delayed packs of pulses.

The bus 9 to the input of the device serves a packet of pulses of positive polarity, the bus 10 - synchronizing pulses that coincide in phase and frequency with the pulses in the packs.

The device works as follows.

In the initial state, the output of the trigger 8 is a low voltage level (level "O"), a high voltage level (level 1) at the output of the elements AND NOT 5, 6 and tires 11, 12.

The first impulse of the pack enters the input of the device via the bus 9, passes through the inverter 2 and goes through the bus 13 to the node 1, which is delayed by a time equal to one pulse repetition period in the pack. The leading edge of the first pulse of positive polarity that occurs on the output bus 14 of the node 1 delay, coincides in time with the leading edge

the second pulse of the stack, and the conditions for the operation of the element AND-NOT 4 are created. At the moment of opening the element AND-NOT 4, the output level "0" appears, which is converted by the inverter 3 to the level "1" and applied to the input of the element AND-NE 7 A second level is also applied to the second input of the NAND 7 element, so it opens and the first burst of the stack is output to the output bus 11, which is delayed by one pulse period in the burst.

At the same time on the output pulse trigger 8 switches, at its output level is set to "1". The same level is maintained at the output of the element AND-NOT 6 due to the level "0" from the output of the element AND-NOT 7. At the end of the second pulse on the bus 9, the elements of the NE-4 and 7 will close. At the moment the third pulse of the packet appears on bus 9 the element AND-NOT 4 is again triggered, however, the element AND-NO 7 does not work, since at its second input there will be a level "0" from the output of the element AND-NOT 6

At the moment when the last impulse of the bundle appears at the output of node 1 of the delay, the AND-NOT 4 element does not work due to the fact that at its second input from the bus 9 there will be a level "0", but conditions will be created for the opening of the AND-HE element 5, since in the absence of a pulse on the bus 9 at the output of the inverter 2 level "1". A pulse of negative polarity (level "0") from the output of the element AND-NO 5 is fed to the output bus 12 and sets the trigger 8 to its original state, in which the element AND-HE 7 becomes ready for operation from the first delayed pulse of the next pack.

Thus, regardless of the number of pulses in a burst, the device selects the first and last pulses delayed relative to their arrival at the input for one pulse repetition period inside the burst.

The proposed technical solution compared to lime provides. significant simplification of the device. The amount of equipment in it does not depend on the number of pulses in the packs.

Claims (1)

Claim A device for inserting the first and last pulses in a stack, containing three elements AND-NOT and a trigger, whose inputs are connected to the outputs of the first and second elements AND-NOT, characterized in that, in order to simplify the device and expand its scope / entered into it the delay node, two inverters and the fourth element. AND-NOT, with the first input of the first element five 760425 6 The NAND is connected to the output of the first inverter and the first input of the delay node, the second input of which is connected to the first input of the device, and the output to the second input of the first NAND element and the first input of the third AND NAND element, the second input of which is connected to the second input of the device and to the input of the first inverter, and the output through the second inverter is connected to the first input of the second element NAND, the second input of which is connected to the output of the fourth element Y-NOT, the first input of which is connected to the output of the trigger, the second - to the output of the second element Y-NOT. five