SU758256A1 - Storage monitoring device - Google Patents

Description

The invention relates to storage devices.

‘Known devices for monitoring memory, containing a firmware 5 machine, five registers, three buffer registers, the inputs of which are connected to a computer [1]. .

The disadvantage of such devices is the inability to effectively control high-speed semiconductor random access memory devices.

Closest to the invention in technical essence is a device for monitoring memory, comprising a buffer register, a local control unit, a driver for write-read signals, a driver for test signals, the first and second 20 address registers, a switch, a number register, and a comparison circuit, ^- "input buffer register connected to an input device, one of the outputs - to the first input unit 25 controlled local Lenia, -second input of which is connected to the output of the comparison circuit having a first input connected to the output register numbers, whose input is connected with. the control input of the device E ² ] · 30

The disadvantage of this device is the inability to check the memory blocks at frequencies higher than the frequency obtained from an external device, such as a computer, which reduces the reliability of the control 'high-speed memory.

The purpose of the invention is to increase the speed of the device and the reliability of memory control.

This goal is achieved in that the device contains a pulse generator, a frequency divider, a group of signal analysis blocks, first, second and third triggers, and the output of the local control unit ^is connected to the input of the pulse generator, the output of which is connected to the input of the frequency divider, the outputs of which and others the outputs of the buffer register are connected respectively to the inputs of the signal analysis blocks, the outputs of one of which are. ryh connected to the mounting vhoda- 'mi triggers avyhody other - to the inputs of address registers, output ^- ~ first flip-flop is connected to an input of the zapisischityvaniya signals, a second flip-flop output coupled to the first input kommutato758256 pa, second and third inputs of which are connected respectively to the outputs of the first and the second address registers, the output of the third trigger is connected to the input of the test signal shaper, the first output of which is connected to the second input of the comparison circuit, ³ outputs of the signal shaper / write-sc and the switch and the second output of the test signal generator are the control outputs of the device ..

The signal analysis unit contains a “encoder, AND elements, an OR element, (the decoder input being connected to one of the inputs of the signal analysis unit, the decoder outputs are connected to 15 yen, respectively, with the first inputs .....

by AND elements, the second inputs of which are connected to other inputs of the signal analysis block, and the outputs - to the inputs of the OR element, the output of which is 20 connected to the Output of the signal analysis block.

In FIG. 1 shows a block diagram of the proposed device? in FIG. 2 is a block diagram of a signal analysis unit; in FIG. 3 - time diagrams of the operation of the device.

The device comprises (Fig. 1) a frequency divider 1, first 2, second 3 third third 4 triggers, driver 5 for write-read signals, switch 6, first 7 and second 8 address 30 registers, driver 9 test signals, 10 pulse generator, local control unit 11, signal analysis units 12-19, buffer register 20, number register 21, 35 comparison circuit 22. The input of the register 20 is connected to the block 23 of the external memory. One of the outputs of the buffer register 20 is connected to the first input of the local control unit 11 _h , the second to the input of which is connected to the output of the comparison circuit 22, and the output is connected to the input of the pulse generator 10, whose output _ is connected to the input of the divider, for 1 frequency. Other outputs of the buffer register 20 and the outputs of the frequency divider 1 are connected respectively to the inputs of the signal analysis blocks 12-19.

(catch) YYHODY One of which are connected to the trigger installation inputs ·

2,3, and 4, and the outputs of others to the inputs of the address registers 7. ' and 8. The output 'of the first trigger 2 · is connected to the input of the driver 5 of the write-read signals. The output of the second trigger 3 is connected to the first 35 input of the switch 6, the second and third passages of which are connected respectively to the outputs of the first 7 and second 8 address registers, the output of the third trigger 4 is connected to the input 60 of the shaper 9 test signals. The first input of the comparison circuit 22 is connected to the output of the register number 21, and the second input to the first output of the shaper 9 test signals, the output of the switch 6 and the output of the shaper 5 are connected to the control outputs of the device. The input of the 21st register is connected to the control input of the device.

The signal analysis block (Fig. 2) contains a decoder 24, elements AND 25 and an element OR 26. The input of the decoder 24 is connected to one of the inputs of the signal analysis block, the outputs of the decoder 24 are connected to the first inputs of the elements AND 25, the second inputs of which are connected to other inputs of the block signal analysis, and the outputs to the inputs of the element OR 26, the output of which is connected to the output of the signal analysis unit.

On Fig. 3 shows a sequence of write-read signals (diagram 1), a sequence. test signals 1 and 0 (diagram 2) for a test of the pair write-read type, the signals generated by the generator 10 ', the following signals with an operating frequency ί (.diagram 5), the triggering signals 1 and 0 generated by the frequency divider 1 and the signals' add 1 to address registers 7 and 8 (diagrams

6-16), as well as the output signals of triggers 2,3 and 4 (diagrams 17, 18 and 19, respectively).

We will consider the operation of the device using the example of monitoring a memory block by a test of the pair-write-read type. This test assumes the presence of zero source information for all bits of all layers of the memory block. Writing unit information to a word with address A <, reading zero information from a word with address, writing zero information to a word with address Αΐ, reading zero information from a word. With address A], and ϊ = 1,2,3, .. .

'N, D = 1,2,3 ,,. ., Ν and! / Г, where N is the number of information layers of the block of the memory being checked. The generator 10 pulses generates pulses with a frequency ί., Corresponding to the working frequency of the tested memory block (diagram. 5) 7 --...... f /. _;

A frequency divider 1 divides the frequency, ί and at the output generates pulses following with a frequency

- £ I and, where η = 1, 2,3,. . ., Ν, as well as pulses delayed relative to the main ones on the QD, where m - 1 | £,.

K = 1,2,3, ..., Ν-1 (see, Fig. 3, diagrams 6-16). Timing diagrams (FIG. 3) are given for the case of checking a memory block containing N = 4 Information words.

The buffer register 20 is used to store information about the number of the element Y 25 connected in each signal analysis block. Information on the buffer register can be recorded from any external [information carrier 758256 of block 2 3 of the external memory, in particular from punched tape, each of which contains information about the number of the connected element And 25 for various monitoring tests. Information from external memory 23 is used 5 to create permanent enable or disable potentials.

The decoder 24 of each block 1219 signal analysis decodes the state of the corresponding bits (θ 'of the buffer register 20 and generates a time <decisive signal to one of the elements And 25, transmitting signals of the corresponding frequency, which through the element OR 26 are fed to the fixed, g input inputs of triggers 2 , 3 and 4. At the inputs of trigger 2, signals are sent to set it to states 0 and 1 with a frequency of £ / 2.

Trigger 2 controls the form_. Lemma 5 of write-read signals. 20 When it is in one of the two states, the shaper 5 outputs a write operation signal to the memory block being checked, in the other, the Read operation signal; thus, at the output of the shaper 5, write-read operations change corresponding to the pairwise write test -Reading (see Fig. 3, diagram 1). . thirty

Trigger 3 controls the switch 6, connecting to the output of the device or the first 7 ,. or the second 8 address registers. Shaper 9 test signals, depending on the state of trigger 4, generates a signal at the output that corresponds to either single or zero test information. Blocks 14 and 17 <signal analysis pass signals to the inputs of the address registers 7 and 8 with a frequency corresponding to the frequency; adding 1 to these registers (see Fig. 3, diagram 1). Depending on the status of the discharges of the buffer register 20, the necessary test signals are generated at the control outputs of the device (at the output of block 9) the outputs of the corresponding address registers 7 or 8 are connected and change operations Write-read-. ⁰ vanye. (at the output of block 5).

When reading, the read information arrives at the input of the register of the 21st day, is compared by the comparison circuit 22 with the recorded test information 55, and, if they do not match, a stop signal is generated at the output of the comparison circuit 22.

The technical and economic advantages of the described device are that the frequency of the signals generated by the generator 10 does not depend on • the parameters of the external memory unit 23 and the buffer register and. therefore, 65 can be set to any technically feasible value, which increases the speed of the device and the reliability of the control and allows ^{one to} control high-speed random access memory devices.

Claims (2)

Claim 1. A device for monitoring memory, containing a buffer register, a “local control unit, a signal-read-out signal generator, a test signal generator, the first and second address registers, a switch, a number register, a comparison circuit, and the buffer register input is connected to the input of the device, one of the outputs to the first input of the local control unit, the second input of which is connected to the output of the comparison circuit, the first input of which is connected to the output of the number register, the input of which is connected to the control input of the device, which, in order to increase the speed of the device and the reliability of control, it contains a pulse generator, a frequency divider, signal analysis blocks, first, second and third triggers, and the output of the local control unit is connected to the input of the pulse generator, the output of which is connected to the input a frequency divider whose outputs and other outputs of the buffer register are connected respectively to the inputs of the signal analysis blocks,. the outputs of some of which are connected to the installation inputs of the triggers, and the outputs of others to the inputs of the address registers, the output of the first trigger is connected to the input of the write-read signal generator, the output of the second trigger is connected to the first input of the switch, the second and third inputs of which are connected respectively to the outputs the first and second address registers, the output of the third trigger is connected to the input of the test signal shaper, the first output of which is connected to the second input of the comparison circuit, the shaper outputs, the signal a recording and read-switch and the second output test signal generator is connected to the control device outputs. 2. Device pop. 1, characterized in that the signal analysis unit contains a decoder, elements AND, an OR element, the decoder input being connected to one of the inputs of the signal analysis unit, the decoder outputs are connected respectively to the first inputs of the AND elements, the second inputs of which are connected to other inputs of the signal analysis unit, and the input inputs are connected to the inputs of the OR element, the output of which connected to the output of the signal analysis unit. -