SU756401A1 - Device for conversion of numbers of residual class system code into binary code and vice versa - Google Patents

Description

The invention relates to the field of computing and can be applied in devices for processing and transmitting digital information.

A device is known for converting numbers from the code of a system of residual ⁵ classes into a binary code whose disadvantage is the impossibility of an inverse transformation.

The closest to this invention is a device for direct and inverse conversion of numbers from the code of the system of residual classes to binary code and, - containing (P + 1) counters (P is the number of bases of the system of residual classes), the outputs of which are connected to the first inputs P + 1) comparison circuits, the other inputs of which are connected to the outputs (n + 1) of registers, the output of the first comparison circuit is connected to one input of the switch, the other input of which is connected to the output of the multi-input element I, whose inputs are connected to the outputs of other circuits By comparison, the inputs

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The counters are connected to the output of another element, the inputs of which are connected to the clock bus and the trigger output, the inputs of which are connected to the start bus and the output of the switch.

A disadvantage of this device is the presence of a large amount of equipment.

The aim of the invention is to simplify the device.

To achieve this goal, a device for direct and inverse conversion of numbers from the code of the system of residual classes to a binary code that contains (n + 1) a counter, two elements AND, the first trigger and a switch, with ··> the single output of the first trigger connected to the first input of the first element I, the second input of which is connected to the clock bus of the device, and ¹ output is connected to the inputs of counters, the output of the second element I is connected to the first input of the switch, the output of which is connected to zero input of the first trigger—

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Pa, the unit input of which is connected to the device start bus, contains the second trigger and (n + 1) zero decoders, the inputs of which are connected to the outputs of the respective counters, the outputs n of the zero decoders connected to the inputs of the second element I the zero decoder is connected to the second input of the switch, the zero and single inputs of the second trigger are connected to the first and second control buses of the device, respectively, the zero output of the second trigger is connected to the input of the addition control and the first counters and the control input by subtracting (n + 1) —th counter, the single output of the second trigger is connected to the input of the subtraction control and the first counters and the input of the addition of the (n + 1) -th counter.

The drawing shows a block diagram of the proposed device.

The device contains a trigger 1, reversible counters 2, 3 _1ί , 3 ^,. . . , Sn,

zero decoders 4 ₄ , 4d,. . . , 4 _П14 , switch 5, trigger 6, elements AND 7 to 8. '

Each of the counters 3 ^, 3,

S _p produces an account modulo the corresponding base in the code of the system of residual classes.

The first control bus, the signal to which is supplied when the device operates when converting a number from a binary code to a system code of residual classes, is connected to a single trigger input

1. When the device is operating in this mode, the signal that arrives at the first control. bus, switches trigger 1 to one state, and the signal from its single output prepares counter 2 for operation in the “subtraction” mode, and counters 3 for operation in the “addition” mode. The binary number to be converted is written in counter 2, counters 3 are reset. The signal arriving at the start bus to the single input of the trigger 6, is set to one state and opens the element I 7 through one of the inputs with a signal · from its single output, to the other input of the element 7 and the clock frequency after passing through the element And 7, produce a gradual subtraction in the counter 2 and simultaneously fill the counter 3. At the moment the counter 2 is reset, the zero decoder 4η + ^ works, the signal from the output of which, passing through switch 5, translates trigger b Nya Ullevi state. This stops the flow of clock pulses through the element And 7. In the counters 3, the code of the system of residual classes corresponding to the binary code originally recorded in the counter 2 is registered.

The second control bus, the signal to which comes when the device is used when converting a number from the code of the system of residual classes to a binary code, is connected to the zero input of trigger 1. When the device operates in this mode, the signal received via the second control bus switches trigger 1 to the zero state and the signal from its zero output prepares the counter 2 for operation in the "addition" mode, and the counters 3 for the ₂ θ operation in the subtraction mode.

. . . W _n, the counter 2 is cleared. The signal arriving on the start bus trigger 6 _{25 is} set to one state and allows the passage of clock pulses through the element 7 to the counting inputs of counters 2 and 3. At the time of resetting all counters 3 ^, 3 ^,. , , 3η,

₃ θ working in subtraction mode, the zero decoders 4 ^, 4 ^, work. . .

4β, the signals from the outputs of which, acting on the inputs of the element And 8, produce at its output a signal which, passing through the switch, 5 to the zero input of the trigger 6, translates it into the zero state and thereby stops the flow of clock pulses to the counting inputs of the counters 2 and 3 through the element And 7. In counter 2, the binary code of the converted number is registered.

The proposed device has a smaller amount of equipment. than the prototype, since it does not use receiving registers, and instead of comparison circuits. zero decoders are used, which are multi-input elements I.

Claims (1)

Claim A device for direct and inverse conversion of numbers from the code of the system of residual classes to a binary code containing (n + 1) a counter (n is the number of bases of the system of residual classes), two AND elements, the first trigger and switch 756401 A reader, the unit output of the first trigger is connected to the first input of the first element I, the second input of which is connected to the clock bus of the device, and the output is connected to the inputs of counters, the output of the second element I is connected to the first input of the switch, the output of which is connected to the zero input of the first trigger, 'a single input of which is connected to the device launch bus, characterized in that, with the simplification of the device, it contains a second trigger and (n + 1) zero decoders, the inputs of which are connected to the outputs of the corresponding counter c, you—, 5 strokes P of the zero decoders are connected to the inputs of the second element I, and the output (l + 1) of the zero decoder is connected to the second input of the switch, zero and single inputs of the second trigger connected to the first and second control bus devices, respectively, zero output of the second trigger ₅ to the input of the addition control and the first counters and the input of the subtraction control (n + 1) -th counter, the unit output of the second trigger is connected to the input of the subtraction control and the first 50 counters and the input of the addition control (n + 1) _ of the counter.