SU752330A1

SU752330A1 - Number comparing device

Info

Publication number: SU752330A1
Application number: SU782646542A
Authority: SU
Inventors: Борис Николаевич Павлов; Евгений Егорович Парисенков
Original assignee: Предприятие П/Я А-3759
Priority date: 1978-07-17
Filing date: 1978-07-17
Publication date: 1980-07-30

Description

Изобретение относится к автоматике^ вычислительной технике и может быть использовано при технической реализации сравнения чисел в устройствах автоматического контроля и управления.The invention relates to automation ^ computer technology and can be used in the technical implementation of comparison of numbers in devices for automatic control and management.

Известно устройство для сравнения чисел, содержащее параллельный (п+1)разрядный сумматор, элементы И, ИЛИ, НЕ. Это устройство обеспечивает приближённое сравнение на основе операции выпитания £1J .A device for comparing numbers is known, comprising a parallel (n + 1) bit adder, AND, OR, NOT elements. This device provides an approximate comparison based on the drinking operation of £ 1J.

Недостатком этого устройства является то, что оно не обеспечивает формирование сигналов Больше, Меньше, необходимых для автоматической подстройки контролируемого объекта.The disadvantage of this device is that it does not provide the formation of signals More, Less, necessary for automatic adjustment of the controlled object.

Наиболее близким к предложенному техническим решением является устройство для сравнения чисел, содержащее сумматор, элементы И, ИЛИ, НЕ, причем первая группа входов сумматора соединенная с входными шинами первого числа, а его вторая группа входов через элементыClosest to the proposed technical solution is a device for comparing numbers containing an adder, AND, OR, NOT elements, the first group of inputs of the adder connected to the input buses of the first number, and its second group of inputs through elements

НЕ - с входными шинами второго числа, выходы всех разрядов сумматора соединены с первыми входами элементов ИЛИ первой группы и парез элемент НЕ - с первыми входами элементов ИЛИ второй группы, причем ко вторым входам элементов ИЛИ первой и второй групп подключены входные шины поля допуска соответствующих разрядов, а выходы элементов ИЛИ первой и второй групп соединены со входами первого и второго элементов И соответственно, управляющие входы которых подключены к шине разрешения, а выходы — ко входам элемента ИЛИ, выход которого соединен с выходной шиной устройства и через элемент НЕ - первыми входами третьего и четвертого элементов И, выходы которых подключены к выходным цщнам устройства, а вторые входы соединены с шиной разрешения, выход переносов сумматора подключен к третьему входу третьего элемента И и через элемент НЕ - к третьему входу четвертого элемента И [2^ .NOT - with input buses of the second number, the outputs of all bits of the adder are connected to the first inputs of the OR elements of the first group and pares the element is NOT - with the first inputs of the OR elements of the second group, and the input buses of the tolerance field of the corresponding bits are connected to the second inputs of the OR elements of the first and second groups and the outputs of the OR elements of the first and second groups are connected to the inputs of the first and second AND elements, respectively, whose control inputs are connected to the resolution bus, and the outputs to the inputs of the OR element, the output of which is connected to the output bus of the device and through the element NOT by the first inputs of the third and fourth elements And, the outputs of which are connected to the output circuits of the device, and the second inputs are connected to the enable bus, the carryover output of the adder is connected to the third input of the third AND element and through the element NOT to the third input the fourth element AND [2 ^.

Недостатком этого устройства является То, что для обеспечения правильной работы устройства код поля допуска устанавливается дискретно, т.е. Δ = 0,1,3,7, ... 2^П*-1 единиц младшего разряда, где Δ - допуск, а η “ разрядность сравниваемых чисел а и ⁵Ъ . Устройство не обеспечивает приближенное сравнение с точностью 2,4,5,6,8 ... и т.д, единиц младшего разряда.The disadvantage of this device is that in order to ensure the correct operation of the device, the code of the tolerance field is set discretely, i.e. Δ = 0,1,3,7, ... 2 ^П * -1 units of the least significant bit, where Δ is the tolerance, and η is the capacity of the compared numbers a and ⁵ b. The device does not provide an approximate comparison with the accuracy of 2,4,5,6,8 ... etc, units of the lower order.

Цель изобретения - расширение диапа- ₁₀зона задания допусков.The purpose of the invention is the expansion of the range - ₁₀ zone for setting tolerances.

Поставленная цель достигается тем, что в устройство для сравнения чисел, содержащее первый сумматор, первая группа входов которого соединена со ¹⁵ входными шинами первого числа, а втсьэая группа входов первого сумматора подключена к выходам группы элементов НЕ, входы которых соединены со входными шинами второго числа, элементы И, ИЛИ, НЕ, причем выход первого элемента И соединен с первым входом первого элемента ИЛИ, выход которого подключен к первому входу второго элемента И и че- ₂₅рез первый элемент НЕ соединен с первыми входами третьего и четвертого элементов И, выход переносов первого сумматора подключен ко второму входу третьего элемента И и через второй элемент НЕ соединен со вторым входом четвертого элемента И, второй вход второго элемента И и третьи входы третьего и четвертого элементов И подключены ко входу управления устройства введены второй сумматор, третий элемент НЕ и η формирователей сигналов передачи, причем выход суммы j -го разряда сумматора, где i =1,2,,.., η соединен с первым входом i -го формирователя сигналов 'передачи, выход которого подключен к первому входу i -го разряда второго сумматора, выходы суммы которого соединены со входами первого элемента И, выход переноса первого сумматора подключей ко вторым входам и через третий элемент НЕ - к третьим входам всех формирователей сигналов передачи, вторые входы всех разрядов второго сумматора соединены с входными шинами соотпетст— вующих разрядов допуска, выход переноса второго сумматора подключен ко второму входу первого элемента ИЛИ и тем, что в нем формирователи сигналов передачи состоят из двух элементов И, элемента ₅₅ИЛИ и элемента HE_t причем второй вход формирователя сигналов передачи подключен к первому входу первого элемента И, выход которого соединен с первым входом элемента ИЛИ, третий вход формирователя 'сигналов передачи подключен к первому , входу второго элемента И, выход которого соединен со вторым входом элемента ИЛИ, выход которого подключен к выходу формирователя сигналов передачи, первый вход формирователя сигналов передачи соединен со вторым входом второго элемента И и через инвертор - со вторым входом первого элемента И.This goal is achieved by the fact that in the device for comparing numbers containing the first adder, the first group of inputs of which are connected to ¹⁵ input buses of the first number, and the second group of inputs of the first adder is connected to the outputs of the group of elements NOT, the inputs of which are connected to the input buses of the second number, AND, OR, NOT elements, and the output of the first AND element is connected to the first input of the first OR element, the output of which is connected to the first input of the second AND element and through _{25 the} first element is NOT connected to the first inputs of the third and of the fourth element And, the carryover output of the first adder is connected to the second input of the third element And and through the second element is NOT connected to the second input of the fourth element And, the second input of the second element And the third inputs of the third and fourth elements And are connected to the control input of the device, the second adder is entered, the third element is NOT and η of the transmit signal shaper, and the output of the sum of the jth digit of the adder, where i = 1,2 ,, .., η is connected to the first input of the i-th signal shaper 'transmission, the output of which is connected to the first input i-th category of the second adder, the outputs of the sum of which are connected to the inputs of the first element And, the transfer output of the first adder is connected to the second inputs and through the third element NOT to the third inputs of all transmitters of the transmission signals, the second inputs of all bits of the second adder are connected to the input buses - leading tolerance bits, the transfer output of the second adder is connected to the second input of the first OR element and the fact that in it the transmit signal shapers consist of two AND elements, an OR element _55, and an HE _t element, and the second input of the transmit signal shaper is connected to the first input of the first AND element, the output of which is connected to the first input of the OR element, the third input of the transmit signal shaper 'is connected to the first input of the second AND element, the output of which is connected to the second input of the OR element, the output of which is connected to the output of the shaper of transmission signals, the first input of the shaper of transmission signals is connected to the second input of the second element And through the inverter to the second input of the first element I.

На чертеже изображена блок-схема устройства.The drawing shows a block diagram of a device.

Устройство содержит сумматор 1, группу элементов НЕ 2< , , ... , 2п формирователей Зр 3₂, З_а, ...З_п, сигналов передачи, каждый из которых состоит из элементов 4 И, элемента 5 НЕ, элемента 6 И, элемента 7 ИЛИ, элемент- 8 НЕ, сумматор 9, элемент 10 И, элемент 11 ИЛИ, элемент 12 И, элемент 13 НЕ, элементы 14 и 15 И, элемент 16 НЕ, вход 17 управления, выходные шины 18, 19 и 20 устройства.The device contains an adder 1, a group of elements NOT 2 <,, ..., 2n formers Зр 3 ₂ , З _а , ... З _п , transmission signals, each of which consists of elements 4 AND, element 5 NOT, element 6 AND , element 7 OR, element 8 NOT, adder 9, element 10 AND, element 11 OR, element 12 AND, element 13 NOT, elements 14 and 15 AND, element 16 NOT, control input 17, output buses 18, 19 and 20 devices.

Устройство работает следующим образом.The device operates as follows.

На вход сумматора 1 поступает двоичный код первого числа (а ) и через группу элементов 2 НЕ - код второго числа (Ь ). В результате сложения пряного кода числа а и обратного кода числа Ъ на выходе сумматора 1, работающего с циклическим переносом, формируется код числа с = ά - Ь и сигнал на шине переноса Р_{п + 1} . Код числа с поступает на формирователи Зр 3₂, 3^ сигналов передачи, на выходе которых формируется обратный код модуля числа (С).The binary code of the first number (a) is received at the input of adder 1 and, through the group of elements 2, NOT is the code of the second number (b). As a result of adding the spicy code of the number a and the inverse code of the number b, the code of the number c = ά - b and the signal on the transfer bus P _{n + 1 are} formed at the output of the adder 1 working with cyclic transfer. The code number c goes to the shapers Зр 3 ₂ , 3 ^ of the transmission signals, the output of which is the inverse code of the module of the number (C).

С выхода формирователя 3j, 32,...,3^ сигналов передачи число (с) поступает на вход сумматора 9, на другие входы которого поступает двоичный код поля допуска d . В результате операции .сложения d + (с) на выходе сумматора 9, работающего с циклическим переносом, формируется код числа E = d+(c) и знакц,^^' на шине переноса. ЕслиЗ>(с), тоф^₊|=1 и на выходе элемента 11 ИЛИ формируется сигнал 1, При наличии разрешения на входе 17 управления на выходе 18 устройства формируется сигнал Норма.From the output of the shaper 3j, 32, ..., 3 ^ of the transmission signals, the number (s) goes to the input of the adder 9, the other inputs of which receive the binary code of the tolerance field d. As a result of the operation of addition d + (c) at the output of the adder 9 operating with cyclic transfer, a code of the number E = d + (c) and sign, ^^ 'are formed on the transfer bus. If S> (s), then ^ ^ ₊ | = 1 and the signal 1 is formed at the output of the 11 element OR. If there is permission at the control input 17, the Norm signal is generated at the device output 18.

Если8=(с), то δ { - = ... =(?_η= 1 иIf 8 = (s), then δ {- = ... = (? _Η = 1 and

Яп + i ~ θ· ^ПР^{И этом на} выходе элемента 10 И формируется сигнал 1, который через элемент 11 ИЛИ поступает на вход элемента 12 И. При наличии сигнала разрешения на входе 17 управления на выходе элемента 12 И и выходе 18 устройства формируется сигнал 1 - Норма.Яп + i ~ θ · ^П Р ^{And this} produces a signal 1 ^{at the} output of element 10 AND, which is fed through element 11 OR to the input of element 12 I. If there is a permission signal at the control input 17 at the output of element 12 And and output 18 of the device, a signal is generated 1 - Norm.

Одновременно сигнал 1 с выхода элемента 11 ИЛИ через элемент 13 НЕ блокирует работу элементов 14 и 15 И. При отсутствии сигнала с выхода элемента 11 ИЛИ и при наличии сигнала *1 на входе 5 17 управления сигнал с шины переноса Р η + 1 сумматора 1 управляет работой элементов 14 И и 15 И. Если а > Ъ , то Р_П41 =1 и на выходе элемента 14 И формируется сигнал 1, на выходе 19 10 устройства формируется сигнал Больше'.:At the same time, signal 1 from the output of element 11 OR through element 13 DOES NOT block the operation of elements 14 and 15 I. If there is no signal from the output of element 11 OR and if there is a signal * 1 at control input 5 17, the signal from the transfer bus P η + 1 of adder 1 controls operation of elements 14 I and 15 I. If a> b, then P _П4 1 = 1 and signal 1 is formed at the output of element 14 AND, signal More 'is generated at the output 19 10 of the device .:

— Если А < Е> , то Р _{п +}1 = О, через элемент 16 НЕ на выходе элемента 15 И и выходной шине 20 формируется сиг- и нал Меньше.- If A <E>, then P _{n +} 1 = O, through the element 16 NOT at the output of the element 15 And and the output bus 20, a signal is generated Less.

Устройство позволяет сравнивать числа, представленные И - разрядным двоичным кодом, с учетом допуска, который может быть представлен любым двоичным числом разрядности не более п .The device allows you to compare the numbers represented by AND - bit binary code, taking into account the tolerance, which can be represented by any binary bit number of not more than n.

Claims

The invention relates to automation and computing and can be used in the technical implementation of the comparison of numbers in automatic control and monitoring devices. A device for comparing numbers is known which contains a parallel (n + 1) bit adder, AND, OR, NOT elements. This device provides an approximate comparison based on the subtraction operation 1. A disadvantage of this device is that it does not provide the formation of signals More, Less necessary for automatic adjustment of the object being monitored. The closest to the proposed technical solution is a device for comparing numbers containing an adder, elements AND, OR, NOT, the first group of inputs of the adder being connected to the input buses of the first number, and its second input group through the elements NOT to the input buses of the second number , the outputs of all bits of the adder are connected to the first inputs of the OR elements of the first group and through the element NO to the first inputs of the OR elements of the second group, and the input busbars are connected to the second inputs of the elements or the first n of the second group the tolerances of the corresponding bits, and the outputs of the elements or the first and the second groups of the groups are connected to the inputs of the first and second elements AND, respectively, whose control inputs are connected to the resolution bus, and the codes to the inputs of the OR element, whose output is connected to the output bus of the device and through the element NOT - the first inputs of the third and fourth elements And, the outputs of which are connected to the device’s output, and the second inputs are connected to the resolution bus, the totalizer output is connected to the third input of the third element And to cut element NOT - to the third input of the fourth element And 23. A disadvantage of this device is that to ensure correct operation of the device, the tolerance field code is set discretely, i.e. D 0,1,3,7, .. units of the lower order, where L is the tolerance an ™ and the width of the compared numbers a b. The device does not provide an approximate comparison with an accuracy of 2,4,5,6,8 and gd, the youngest category. The purpose of the invention is to expand the range of tolerances. The goal is achieved by the fact that the device for comparing numbers, containing the first adder, the first group of inputs of which is connected to the input buses of the first number, and the second group of inputs of the first adder is connected to the outputs of the group of elements NOT whose inputs are connected to the input and buses of the second number, elements AND, OR, NOT, and the output of the first element AND is connected to the first input of the first element OR, the output of which is connected to the first input of the second element AND and through the first element is NOT connected to the first inputs of the third and And the first output of the first sum of the mat is connected to the second input of the third element And through the second element is NOT connected to the second input of the fourth element And, the second input of the second element And and the third inputs of the third and fourth elements And connected to the control input of the device entered the second adder, the third element is NOT and P signal transmitters, and the output of the sum of the t-th digit of the adder, where 1,2, ..., p, is connected to the first input of the transmit signal generator, the output of which is connected to the first input th bit of the second adder, the sum of whose outputs are connected to the inputs of the first element I, the transfer output of the first adder is connected to the second inputs and through the third element NOT to the third inputs of all formers of the transmission signals, the second inputs of all the bits of the second adder are connected to the input clays of the corresponding tolerance bits, the transfer output of the second adder is connected to the second input of the first OR element, and the fact that the transmitters of the transmission signals consist of two AND elements, the OR element and the NOT element, and The second input of the transmission signal generator is connected to the first input of the first element AND, the output of which is connected to the first input of the OR element, the third input of the transmission signal generator is connected to the first input of the second element AND, the output of which is connected to the second input of the OR element, the output of which is connected to the output of the imager the transmission signals, the first input of the transmission signal generator is connected to the second input of the element I, and the inverter is connected to the second input of the first element I. The drawing shows the block diagram of the device. The device contains an adder 1, a group of elements HE 2, 2, ..., 2P of the formers 3, 32, 3, ..., 3, transmission signals, each of which consists of elements 4 AND, element 5 NOT, element 6 AND, element 7 OR, element 8, NOT, adder 9, element 1O AND, element 11 OR, element 12 AND, element 13 NOT, elements 14 and 15 AND, element 16 NOT, control input 17, output buses 18, 19 and 20 devices. The device works as follows. A double code of the first number (s) is fed to the input of summat ea 1 and through the group of elements 2 NOT the code of the second number (b). As a result of the addition of a straight code of the number a and the inverse code of the number b at the output of the adder 1, working with cyclic transfer, the code of the number with d - b and the signal on the transfer bus Pp.j are formed. The code of the number comes to the shapers 3, 3, ..., 3 transmission signals, at the output of which the reverse code of the number module (C) is formed. From the output of the imaging unit 3, 3i2 ,,,, 3 transmission signals, the number (s) is fed to the input of the adder 9, to the other inputs of which the binary code of the tolerance field d is received. As a result of the operation d + (c) at the output of the adder 9 working with cyclical transfer, a code of the number E (+ (c) and signs, | on the transfer bus. Eclid (c}, ToQj., l and at the output of element 11 OR is generated OR signal 1 is generated. If there is permission at the control input 17 at the output 18 of the device Norma signal is formed. If c (c), then B 2 p 1 and Yp - + - 1 this on the code of element 10 And a signal is formed, through the element 11 OR is fed to the input of element 12 I. If a permission signal is present at input 17 of control at the output of element 12 I, a signal 1 - Normal is generated at device output 18. Simultaneously, the signal from the output of element 11 OR through element 13 does NOT block the operation of elements 14 and 15 And, If there is no signal from the output of element 1 OR, and if there is a signal at the control input 17, the signal from the transfer bus is R p + I s; adder 1 controls the operation of elements 14 AND and 15 I. If a b, t RFCR i 1 and the output of the element 14 And the signal I is formed, at the output 19 of the device a signal is generated More - If A-iB ,, through the element 16 is NOT at the output of the element 15 And and the output bus 20, a signal Less is formed. The device allows you to compare the numbers represented by the P - bit binary code, taking into account the tolerance that can be represented by any binary number of digit no more than n. Claim 1. A device for comparing numbers containing a first adder, the first group of inputs of which are connected to the input buses of the first number, and the second group of inputs of the first adder are connected to the outputs of a group of elements whose inputs are connected to the input terminals of the second number, the elements AND, OR, NOT, and the output of the first element AND is connected to the first input of the first element OR, the output of which is connected to the first input of the second element AND; and through the first element is NOT connected to the first inputs of the third and fourth elements AND, the carry output of the first adder is connected to the second input of the third element AND and through the second element is NOT connected to the second input of the fourth AND element, the second input of the second element And and the third inputs of the third and The fourth AND elements are connected to the control input of the device, characterized in that, in order to extend the tolerance setting range, a second adder, a third NOT element, and n formers of the transmission signals are inputted into it, and the output Ummah 4 th bit adder, where 1,2, ... p, is connected to the first input of the signal conditioner, the output of which is connected to the first input of the second digit of the second adder, the output of the sum of which is connected to the inputs of the first element And, the transfer increment of the first adder is connected to the second inputs and through the third element NOT to the third inputs of all drivers of the transmission signal, the second inputs of all bits of the second adder are connected to the input buses of the corresponding tolerance bits, the transfer output of the second adder is connected oromu input of the first OR element. 2, the device according to claim 1, characterized in that the drivers of the transmission signal in it consist of two AND elements, an OR element and a NOT element, and the second input of the transmission signal generator is connected to the first input of the first AND element, which code is connected to the first input of the OR element, the third input of the signal conditioner transmission is connected to the first input of the AND element, the output of which is connected to the second input of the OR element, the output of which is connected to the output of the transmission signal conditioner, the first input of the signalization generator united with the second input of the second element I and through the inverter with the second input of the first element I. Sources of information taken into account in the examination 1. Gavrilov Yu. V., Puchkov A. I. Arithmetic devices of high-speed digital computers. M., Sov. Radio, 1970, p. 253255. 2, USSR Author's Certificate according to Jvfe 2481137 / 18-24, May 20, 1996 (prototype). "Go & gs - - - - p I UJJ). . . b - and PP I L