SU1200404A1 - Switching device - Google Patents

Abstract

A SWITCH containing in each of the n channels a serially connected register and a decoder, as well as a block of AND-OR elements, the output of which is the output of the switch, whose information buses are connected to the first group of inputs of the blocks of AND-OR elements ayu y and so that, in order to expand the functionality, a priority block is inserted into each channel, the control inputs of which are connected to the corresponding outputs of all decoders, and the outputs are connected to the second group of inputs of the block of AND-OR gates s priority of all n blocks are combined and connected to the gating switch bus, wherein n inputs connected to respective registers by the control switch tires.

Description

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The invention relates to a pulse technique, in particular, to electronic switches of digital information, and can be used in communication technology and in computer-aided measuring systems with programmable switching.

The purpose of the invention is to expand the functionality by providing priority service to subscribers and directing several subscribers to a common receiver of information.

FIG. Figure 1 shows the switch flow chart; in fig. 2 is one example of the implementation of the functional block of the priority block.

The switch contains n blocks 1 | , ..., In elements AND-OR, n registers 2 (, ..., 2n, n decoders 3, ..., 3n and n blocks 4 (, ..., 4 ”priority, inputs 5 {,. .., 5 priority block 4, outputs 6, ..., 6 of the priority block, n information buses 7 |, ..., 7, g, n output buses 8 {, ..., n control buses 8 (, ..., 9 and the gate bus 10. The priority block 4 contains n output elements 11 and 11, input elements 12 and 12, or elements 13, n inverters 14.

In each of the n channels, the control buses 9 are connected to the inputs of the register 2, the outputs of which are connected to the inputs of the decoder 3. The outputs 6 of the priority block 4 are connected to the second group of inputs of the AND-OR element 1, the output of which is the corresponding output bus 8 of the device.

Information tires 7,. .., 7, are connected to the corresponding combined first group of inputs of blocks 1,. . . , 1 f, AND-OR elements.

The gate bus 10 is connected to the gate inputs of blocks 4, ..., 4 connected to each other, the priority, the corresponding inputs of which are connected to the corresponding outputs of the decoders 3 ;,,. . . , 3 ,.

Switch. Works as follows.

Let each i-th subscriber's computing system resource) correspond to control buses 9 and device information bus 7. If it is necessary to transmit information from the i-ro subscriber (A;) to the j-th subscriber (A-), then the subscriber A; through

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control tires 9;

carries out

record of the address of the subscriber A; in register 2; . The address is decoded by decoder 3; and at input 5 of block 4 priority

a signal is generated that is fed to the control input j-ro of priority block 4. Unit 4, priority works in such a way that when there are several request signals, some of the inputs 5, -5 serve them in order of increasing. their index numbers.

Suppose that the inputs 5. and 5 received single signals. Then, a single potential level is applied to the gate bus 10 of the device, which is used to memorize requests and single potential levels are formed at the outputs of the OR 13 elements. The elements of the inverter 14 and 14 are included. part of the chain of parallel transfer signal prohibition.

Thus, if the output element OR 13 has a single potential level, it inverts using inverter 14 and prevents the passage of single signals through other elements from the set. Therefore, if there is a zero potential level on the gate bus 10, the first output signal 6 is generated corresponding to the first request received at input 5. After subscriber A has finished transmitting information to the jth subscriber, it is set to register 5 / to the zero state, which is not allowed for decoding, and

output 5 of the decoder 3 (a zero potential level is formed (zero request signal), resetting the unbalanced trigger to the zero state, i.e. the output of the OR element 13 produces a zero potential level which inverts on the inverter 14 and enables the next order of the signal request 5 to enter output 6. Signals at outputs 6 and 6), formed at different time intervals, control the connection, respectively, of the information bus 7 of the subscriber A j and the information bus 71) of the subscriber A to the output bus 8j of the subscriber A using Block G. AND-1SHI.

The presence of zero potential on the gate bus 10 leads

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to the fact that other request signals, which have appeared at the moment of processing the request signals of subscribers A and A, are not stored in the corresponding asymmetrical triggers of the priority block 4j. After the subscribers A and AJ, the information is transmitted to the subscriber A: on the gate bus 10, the potential level changes from zero to one and

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The following sequence of processing new requests is performed in order of increasing their numbers.

Thus, the proposed switch has a wide functionality due to the provision of priority switching of several input buses 7 to one output bus 8.

s,

ffn

Claims (1)

A SWITCH containing in each of the η channels a register and a decoder connected in series, as well as an AND-OR element block, the output of which is an output of a switch, the information buses of which are connected to the first group of inputs η AND-OR element blocks, and with the fact that, in order to expand the functionality, a priority block is introduced into each channel, the control inputs of the second are connected to the corresponding outputs of all decoders, and the outputs to the second group of inputs of the block of AND-OR elements, the gate inputs of all η priority blocks are combined and connected to the gate bus of the switch, and the inputs η of the registers are connected by the corresponding control buses of the switch. SLb 1200404>