SU750565A1 - Buffer storage - Google Patents

Description

(54) BUFFER STORAGE DEVICE

one

The invention relates to computing and can be used in communication technology and computing, in particular for coupling asynchronous sources of intermittent groups of information to an isochronous information receiver.

Buffer memories (BZU) are known that contain number registers, write gates and a write control register in which numbers are written to the number registers by pulses generated by the write control register 1 and 2.

The disadvantage of these devices is the distortion of numbers when they are read by pulses, asynchronous clock pulses of BZU, which prevents the use of these devices in systems with asynchronous reading.

The purpose of the invention is to expand the functionality of the LPU due to asynchronous word reading.

To achieve this goal, the device contains an additional trigger and valve, the first inputs of which are connected to the readout, the output of the additional valve through the main trigger of the last bit of the control register is connected to another input of the additional trigger, whose output is connected to the second input of the additional valve, the third input connected to the clock, the second output of the main trigger of each bit pack, equal to the shift register is connected to the third input of the first valve, the output of which is ene with input of the second gate, the output of the last is connected to the second input of the auxiliary flip-flop, and the output of the third gate of each discharge Con (chen 0 to the first input of the previous main discharge trigger control register write.

The drawing shows a functional diagram of the device on AND-NOT type valves with a push-pull control register.

The device contains t-bit registers of numbers 1 - 1, connected via recording gates 2-2, control register 3 of the record, including the main triggers

20 4-4 connected to the inputs of the first valves 5-5, the outputs of which are connected to the inputs of the second valves 6-6, auxiliary triggers 7-7, the inputs of which are connected to the outputs of the valves 5-5 and

6-6, and the first outputs to the inputs of a third of their valves 8-8 and an additional read trigger 9, connected to the additional read valve 10.

To the inputs of the valves 5 and 6 is connected bus li clock pulses TI. To the inputs of the valves 8 p 10 connected bus 12 clock pulses TI. To the inputs of the valves 2 and 5 is connected 13 records of information. The outputs of the valve 8 are connected to the register. M numbers. To the input of the additional trigger 9 and the valve 10 is connected bus 14 read information, the input of the additional trigger 9 and the output of the additional valve 10 are connected, respectively, to the output and input of the main trigger 4, and the outputs of the valves 5 are connected to the inputs of the valves 2 through inverters 15-15.

The initial state of the control register flip-flops corresponding to the free RAM is a high (single) potential and the absence of such at the upper outputs of the triggers 4 and 7, respectively. In the case when the first reading (after power up) of false words is read, the state of triggers 4 and 7 can be arbitrary and there is no need to install them.

The device works as follows.

Tire clock pulses 11 and 12 continuously receive a series of clock pulses TI1 I.TI2, respectively, out of phase one relative to another. In the initial state, trigger 4 receives high potential from valve 5 and from trigger 9 to valve 10. To write information to the bus 13, a pulse arrives, which, together with the first pulse TI1, via valve 5 and valves 2, writes the first m into the register 1, the bit word, and the auxiliary trigger 7 of the control register simultaneously switches and supplies a high potential to the gate 8. The first pulse TI2 switches valve 4 through valve 8, the latter removes high potential from valve 5 and supplies high potential to valve 52. The second pulse TI1 through valve 5 and valve 2 writes a word to register P, while the trigger 7 of the control register It switches and supplies a high potential to valve 8. The second pulse TI2, through gate 8, resets register 1, switches trigger 4 and 4 so that high and low potentials arrive at valves 5 and 5, respectively.

The cycles described below are repeated and the word is fixed in the p-ohm register.

Information is read, i.e., it is updated in the output register by applying a read pulse to the bus 14. The read pulse confirms the state of flip-flop 9 and goes to gate 10. The first pulse, after a read pulse, is given by the pulse TI2 and triggers flip-flop 4, which gives a high potential on

gate 3 and switches the trigger 9. The latter removes the high potential from valve 10, and thereby blocks the read pulse.

The first year after the reading pulse, pulse TI1, through valve 5 and valves 2, writes a new t-bit word to register 1.

The second impulse TI2 through the valve 8 switches the trigger 4, which removes the high potential from the valve 5 and confirms 0 gives the state of the trigger 9.

The pause between the read pulse and pulses does not turn off the trigger 9, which supplies a high potential to the valve 10, and the read cycle repeats when the next read pulse is applied.

In cases where, due to the asynchrony of the read pulses and the clock pulses, the read pulse overlaps the clock pulse partially, a pulse with a duration (and

 amplitude) insufficient for switching the trigger 4, and the described read cycle is performed by the following clock pulse TI2.

It can be seen from the device that the LPD allows independent recording and reading of information, read pulses and clock pulses of the RAM can be asynchronous, and for reliable operation of the device, the pause between read pulses should be no less than the switching time of the additional trigger, and the read pulse duration should exceed the duration of the clock pulse (with the duty ratio of the latter) or the duration of the pause between clock pulses (with Q 2) by at least the switching time of an additional t rigger, increased by the maximum difference between the on and off times of the additional valve, which does not exceed the on time of the additional valve. The registers of storing W-bit numbers p - 1P-1 can be implemented on RS-, and register 1 - on D-triggers of potential logic. The control register shift BZU. Can be multi-cycle.

Claims (2)

1..BTopcKoe certificate of the USSR L 377887.kl. G 11 From 19/00. 1974. 2..A USSR author's certificate jYo 407396, cl. G 11 C 19/00, 1976 (prototype).