SU739722A1 - Pulse delay device - Google Patents

Description

one

The invention relates to automation and computing, can be applied, in particular, in electronic devices for various purposes where it is necessary to obtain a delay of sequences of pulses.

A device for delaying pulses is known, which contains an input bus, a resistance-capacitive integrating element associated with the inputs of two limit value alarms with different response levels, one logical single-input element, whose input is connected to the output of one of the limit value alarms, and the output with one of inputs of a three-input logic element; its other two inputs are connected respectively to the output of the second limit value detector and to the input bus 1.

The device generates only pulses of a fixed duration, reaching a frequency of no more than some: 5 data, and therefore it cannot be used to delay arbitrary pulse sequences. | This limits the functionality of the device and its scope. In addition, the use of limit value detectors complicates the circuit.

A device for delaying pulses is known, which contains an input bus that is connected to the input of the first delay element, and through an inverter to the input of the second, an asynchronous RS flip-flop on two AND-NOT 2 elements.

Along with positive qualities 10 a small number of elements, sufficiently wide functional possibilities and scope, ease of communication between the elements, this device for delaying pulses has serious disadvantages: it contains differential circuits, which leads to low noise immunity, and also complicates the manufacturing technology in hybrid film execution.

The purpose of the invention is to increase the reliability and processability of the device.

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Claims (2)

The goal is achieved by the fact that a pulse bus device containing an input bus that is connected to the input of the first delay element and through the inverter to the input of the second delay element, an asynchronous RS flip-flop on two IS-NOT elements, introduces an output asynchronous RS- A trigger and two I-NB elements whose outputs are connected to the corresponding inputs of an output RS-trigger, the first input of the first I-NOT element is connected to the output of the first trigger, the first input of which is connected to. the output of the second delay element and the second input of the first NAND element, the first input of the second AND-YE element is connected to the output of the first trigger, the input of which is connected to the output of the first delay element and the second input of the second NAND element. FIG. 1 shows the functionaldiagnostic scheme of the proposed device for delaying pulses; on fi1. 2 - time diagrams of his work. The device for delaying the pulses contains an input bus connected to the input of the inverter 1, the output is copied to the input of the delay element 2; delay element 3, the elements AND-NOT 4 and 5, forming asynchronous | {th RS-flip-flop 6, the output Q and the input Sd of which is connected to the inputs of the first element AND-NOT 7; the second element AND-NOT 8; elements AND-NOT 9 and 10, forming the output asynchronous RS-, TpHrrep 11, the output Q of which is connected to the output of the device for delaying the pulses. The proposed device works as follows. Before applying positive pulses to the input of the device, a single high potential is present at the output of the inverter 1 (diagram 1 in Fig. 2). At the outputs of the elements of delays 2 and 3 (diagrams 2 and 3, Fig. 2) there are high levels of intensity. The delay elements can be made in the form of a one-shot. Assume that both flip-flops are in the state O before the -pulse impulses. At the same time, the output level of the NE-4 element is a low voltage level (diagram 4, fig.2, and the output of the IS-NOT 5 element is high (diagram 5 , Fig. 2), which means the state O of the asynchronous trigger 6. Low potential at output 4 leads to the appearance of a high voltage level at the output of the first element AND-NE 7 (diagram 7, figure 2). At both inputs of the second element The NAND 8 is present with single signals and a zero signal is generated at its output (Figure 8, Fig. 2). At the outputs ale NOV 9 and 10, forming an output asynchronous RS flip-flop And before the impulses are present, respectively, low and high voltage levels (diagrams 9 and 10, Fig. 2) are present, which means the state O of the flip-flop P. 24 the first input pulse at the output of the inverter 1 forms a low potential, after which a low voltage level is formed on the input side of the delay element 2. This signal maintains a high voltage level at the output of the first AND-7 element and sets a high potential at the output AND-- NOT 4. After that to both high voltage levels are applied to the inputs of the AND-NE element 5, and a low potential is formed at its output. This means moving the RS-flip-flop 6 asynchronously from zero to one. A low potential from the output of the NANDI element 5 leads to the appearance of a high signal at the output of the NAND element 8. There are no other changes in the output potentials of the elements of the device at time t. At the end of the delay period of the delay element 2 (moment t), a high voltage level appears at its output, after which high voltage levels are applied to both inputs of the AND - NOT 7 element. This leads to the formation of a zero potential at its output, after which a high potential appears at the output of the AND element 9. High voltage levels from the outputs of the AND-HE elements 8 and 9 cause the formation of a low potential at the output of the i-NE-10 element. Thus, at the time t, the output asynchronous RS flip-flop 11 changes from the zero to the single state. Other changes in the output potentials of the elements of the device at time i. does not occur until the end t of the input pulse. At time t, a single signal is produced at the output of inverter 1, and zero at the output of delay element 3. It confirms a single voltage level at the output of the AND-HE element 8 and causes the formation of a high potential from the output of the AND-HE element 5. Thus, at both inputs of the AND-HE element 4, single repetitions are formed, and a zero signal is formed at its output. This means that the asynchronous RS-flip-flop 6 has entered the state I. Other changes in the output potentials of the elements of the device at the moment tn do not occur. .. At the end of the delay period of the delay element 3 (time C), a high voltage level appears at its output, after which high voltage levels are applied to both inputs of the AND-HE element 8. This leads to the formation of a low potential at its output, after which a high potential appears at the output of the NAND. High levels of voltage from the outputs of the elements AND-II 7 and 10 cause the formation of a low potential at the output of the element AND-NOT 9. Thus, at the time V. the output asynchronous RS flip-flop 1 goes from zero to zero. At time t. all the output signals of the elements of the device for delaying the pulses coincide with their initial states, and then the operation of the device is repeated. It can be seen from the analysis of the work that the device provides a stable and uninterrupted delay of the output signal (output of element 9) relative to the input signal. This allowed us to significantly improve the reliability of the device in the systems of automation and computer technology with high levels of interference on power supply circuits. Claim device A device for delaying pulses, containing an input bus that is connected 2, 6 to the input of the first delay element and, through an inverter to the input of the second delay element, an asynchronous RS flip-flop on Two NAND devices, different from that to increase reliability and manufacturability of the device, the output asynchronous RS-trigger on two elements AND-NOT and two elements AND-NOT, the outputs of which are connected to the corresponding inputs of the output RS-trigger, are entered into it, the first input of the first element AND-NOT is connected to the output of the first th trigger, the first input of which is connected to the output of the second delay element and the second input of the first AND-NOT element. the first input of the second NAND element is connected to the output of the first trigger, the input of which is connected to the output of the first delay element and the second input of the second NAND element. Sources of information taken into account in the examination 1. Germany patent N 2357651, cd. H 03 K 5/13, published 1975. 2. Samoilov LK. Devices for delaying information in a discrete technique. M., Sov. radio, 1973, fig. 1.4 (prototype).