SU736361A1 - Pulse train shaper - Google Patents

Description

I

The invention relates to a pulse technique.

A pulse trainer is known that contains two memory registers with individual input devices, a pulse generator and a block of logic elements for switching registers 1.

The disadvantage of this former is its complexity.

The closest in technical essence to the invention is a shaper comprising a pulse generator, the output of which is connected to the counter input and the first input of a three-input logical element OR, the output of which is. through a logical element is not connected to the first inputs of the two-input logic elements AND, the second inputs of which are connected to the outputs of the trigger trigger and the corresponding inputs of the logical element AND-NOT and the decoder, the output of which is connected to the second input of the three-input logic element

OR, and the output of the logical element IS is NOT connected to the first input of the two-input logic element OR, the second input of which is connected to the input bus and the output is connected to the input of the control of impulse generators 2.

This driver does not provide the possibility of excluding certain groups of pulses in a series.

The purpose of the invention is to increase the number of formative pulse series by eliminating certain groups of pulses.

The goal is achieved by the fact that a pulse series generator containing a pulse generator whose output is connected to the counter input is the first input of a three-input logic element OR whose output is NOT connected to the first inputs of the two-input logic elements I, the second inputs of which are connected with the outputs of the trigger counter and the corresponding inputs of the logical element AND-NOT and the decoder) a, the output of which 37 poro is connected to the second input of the three-to-one logical element OR, and the output of the logical element is NOT connected to the first input of the two-input logic element OR, the second input of which is with the input bus, and the output is connected to the control input of the pulse generator, an additional logic element OR, an additional counter, a prohibition logic element, an additional logic element HJ5 are introduced And the memory element, one output - which is combined with the additional output of the decoder, the second input is connected to the OUTPUT of the additional counter, and the output through the additional logical epemeggg is NOT connected the first input of the logic element is barred, the second input of which is connected to the output of the generator generator, and the output is connected to the input of the additional counter, the outputs of which bits) are connected to the inputs of the d-additional logic element OR the output of which is connected to the third input of the three-input logic element OR . The drawing is a structural electrical driver circuit. It contains a pulse generator 1, a s. Counter of 2 pulses, consisting of triggers 3-5, a logical element AND-NOT €, a logical element OR 7, logical elements AND 8-10, a decoder 11, a logical element NOT 12, a logical element cop or 13, doyolpetily ogiy element. OR 14, counter 15,. a ban 16, a logical element NOT 17, memory element 18. A controlled signal is applied to hippg 19, the Former operates as follows. Impudes from the output of the generator 1 are fed to the input of counter 2. At the output of the trigger trigger 3-5 of counter 2, the state of the alternating state 1 is output. From the outputs of trigger 3-5, pulses arrive at the input of the decoder 11 and to the first inputs of logic elements AND 8-1O Descrambler 11, depending on what combination it is necessary to block, during the presence of this combination at the outputs of triggers 3-5. produces from the first output to the logical eMSi-rr AND / AND 13 and then to the input of the logical element NOT 12, the output of which signal will not be, with the result that this combination of pulses to the output of the device will not pass. On the second input, s 1 of the logical elements AND 8-U comes the signal of the element NOT 12, which gives out the ignition even when the signal from the generator 1 to the counter 2 is not received and when there is no signal from the output of the decoder 11 through the logical element OR 13. So, at the outputs of the logic elements AND 8-10, in the TC signals only when imgguls from generator 1 ends, i.e. Triggers 3-5 will work out this regular impulse and the transient spreads in them will not result in a false combination of pulses. If it is necessary to prohibit the pulse combination series, starting with a certain combination (the beginning of the series), then a signal is output from the second output of the decoder 11 at the moment of the presence of the combination of the start of the series at the outputs of triggers 3-5, which includes memory element 18, and through HE element 17 a ban 16 starts the counter 15 pulses, from the outputs of the cells (not shown) of which the signals through the logic element OR 14 knock on the logic element 13, the output of which has no signal, which leads to the combination of this forbidden signal Rhee pulse will not pass through the AND gates 8-10 for the output device. The memory element 18 is returned to the initial state of w-ie by the signal from the output of the last discharge of counter 15, which corresponds to the ending of the prohibiting series of pulse combinations. The prohibition 16 logic element gives an impulse only at the moment of the presence of signals i at the output of the pulse generator 1. The number of bits in the counter 15 depends on the number of prohibiting combinations in the series. The logic element 6 marks the end of the device operation and stops the generator 1. The device also provides for forced stopping the generator 1 by the action of the logic element OR 7 on the generator. Formula of the invention Shaper of a pulse train containing a pulse generator, whose output is connected to the counter input and the first input of the three-input logic element I.PI, whose output is NOT connected to the first inputs of the two-input logic elements I through the logic element, and the second input is connected to the trigger outputs the counter and the corresponding inputs of the AND gate and the decoder, the output of which is connected to the second input

a three-input logical element OR, and the output of the logical element AND-NOT is connected to the first input of the two-input logical element OR, the second input of which is connected to the input bus and the output connected to the control input of the pulse generator, characterized in this case, an additional logical element OR, an additional counter, a logical element a ban an additional logical Element NOT a memory element, one input of which is connected to an additional output of a desh are entered into it. Rathor, the second

the input is connected to the output of the additional counter, and the output through the additional logic element is NOT connected to the first input of the logic element, the second input of which is connected to the output of the pulse generator, and the output is connected to the input of the additional counter, the outputs of the bits of which are connected to the inputs of the additional logic element OR, the output of which is connected to the third input of the three-input of the logical element OR.

Sources of information taken into account during the examination

1.Patent UK

No. 1278945, class, and ER, 06.21.72.

2.Certificate of Certificate No. 2425625, No. 2489413,

CP H 03 K 3/84, 12/06/76.

Claims (1)

Claim A pulse series generator comprising a pulse generator, the output of which is connected to the counter input and the first input of a three-input logic element OR, the output of which through a logic element is NOT connected to the first inputs of two-input logic elements 738361 6 AND, the second inputs of which are connected to the outputs of the trigger counter and the corresponding inputs the AND gate and the decoder, the output of which is connected to the second input of the three-input OR gate, and the output of the AND gate is NOT connected with the first input of the two-input OR logic element, the second input of which is connected to the input bus ^ the output is connected to the control input of the pulse generator, characterized in that, with the circuit for increasing the number of generated series, an additional OR logic element, an additional counter, and a logic inhibit element are introduced into it an additional logic element is NOT and a memory element, one input of which is connected to the additional output of the decoder, the second input is connected to the output of the additional counter, and the output through the additional the logic element is NOT connected to the first input of the logic element 'for 5 pret, the second input of which is connected to the output of the pulse generator, and the output is connected to the input of an additional counter, the outputs of the bits of which are connected to the inputs of the additional logical element OR, the output of which is connected to the third input of the three-input logic element OR.