SU705521A1 - Read-only memory - Google Patents

Description

(54) PERMANENT STORAGE DEVICE

I

The invention relates to the field of computer technology, in particular, to computer storage devices.

A storage device is known that contains a storage unit, a number register, an address register, a message address decoder, a permanent storage unit, a priority counter, OR elements, a message end decoder, a control unit, a storage unit cell allocation block, a page number decoder, a page number decoder, a counter page converter, reversible counter, the page counter outputs are connected to the page number decoder, the outputs of which are connected to the input of the control unit 1.

The closest technical (purposes: this invention is a permanent storage device (ROM) containing a drive connected. To the outputs of the address decoder, the inputs of which are connected to the outputs of the address register, the outputs of the drive are connected to the inputs of the output register 2.,

A disadvantage of the known device is the inability to perform with its

By means of the priority management mode of the memory hierarchy, implemented in accordance with the selected page removal algorithm.

The aim of the invention is to expand the functionality of the device by implementing the priority control mode.

For this, the device contains the second address register, the second address decoder, the second and third output registers, AND and OR elements, while the outputs of the second

9 of the address register are connected to the corresponding inputs of the second address decoder, the first inputs of the AND elements are with the corresponding outputs of the first output register, and the second inputs are connected with the corresponding outputs of the second address decoder, and the outputs with the corresponding inputs of the OR, OUT. the output register, and the outputs of the second output register are connected to the inputs of the first address register, the inputs of the third output register are connected to the other outputs of the storage device.

The drawing shows a diagram of the proposed permanent storage device.

The device contains a drive I with a numerical ruler 2, the first register 3 addresses, Shiu 4 - setting the first register 3 addresses to its original state, the first decoder 5 addresses, the first output register 6, the third output register 7, the output control bus 8, the second input register 9, input buses 10, second address decoder 11, elements AND 12, elements OR 13, second output register 14.

The corresponding outputs of accumulator 1 are connected to the inputs of the third output register 7 of the page number to be deleted, the outputs of which are connected to the control output buses 8, the outputs of the first output register 6 are connected to the first inputs of elements 12, the second inputs of which are connected to the outputs of the second decoder AND address, the inputs of which are connected to the outputs of the second register 9 with the inputs 10, the outputs of the elements AND 12 are connected to the inputs of the elements OR 13, the outputs of which are connected to the inputs of the second output register 14, and its outputs are connected to moves the first register 3 addresses.

The device is working. in the following way .

Each numerical line 2 of accumulator I is associated with a list of physical pages available in the LPU ordered in accordance with the adopted strategy for determining the deleted page, called in the Further state (the total number of such conditions may be n, where n is the number of pages in - BZU). The numerical ruler 2 itself contains the word descriptor of this state, derived from the number of the page to be deleted, corresponding to this state, and the addresses of new word descriptors, which describe all possible states of the RAM as received by the processor. The number of addresses in the state descriptor word is equal to n, and the i-th address of the descriptive word shows the address of the state to which the current state passes. When a request is received for information in the i-th page. The result of the priority management mode of the hierarchy should be the number of the page, which, if necessary, would need to be deleted. The job of getting it is done in two steps. Consider it for time t 4- I..

In the first step, step 6 is performed to obtain the state in which the LPU will reside in. time t-1, for which, at time t, an address is read that is located on the second output register 14 to the first address register 3, which through the first address decoder 5 determines the numeric line 2 containing the descriptor of the defined state . This state descriptor word is read (by a corresponding control signal, which is not shown in the drawing) to the first output register 6 and the third output register 7 of the page number to be deleted. As a result of this step, the number of the deleted page goes to the output control buses 8. At the second step, at the time t + 1, the preparation for the next cycle of operation of the priority mechanism occurs at the time t -f 2. For this, the logical page number required by the processor is mapped to

 physical page BZU. According to the received physical page number, the transition to the new state takes place by obtaining the address of the new state descriptive word, for which the physical page number goes to the inputs 10 of the second register 9 of the address, the control signals to those elements are issued via the second address address decoder 11 And 12, which correspond to the choice of the address of the word descriptor state, in which the transition occurs

 by the page number arriving at the second register 9 addresses. The selected address of the word descriptor through the elements OR 13 enters the second output register 14.

J By taking action. For example, where p 3, Denote pages of BZU by numbers 1, 2, 3. At each moment of time t the list of these three pages ordered according to the algorithm for selecting the page to be deleted shows the current state of BZU ( be n states). Since, according to the NDI algorithm, the page that was most recently accessed is deleted each time,

5 the first place in the list of pages of the corresponding state is the page number, which was accessed at the immediately preceding moment of time t-1, the second place was the page number that was polled before the above

cf., etc. For page 3, the number of the page standing in third place in the list of pages, which corresponds to the state, indicates that, if necessary, this page is to be deleted. For p 3, possible states and variants of transition from one state to another when the processor accesses the physical pages entering these states may be. 6. So, for example, the state of 1, 2, 3 will not change when the processor accesses the first {) page; when the second page is accessed, it goes to

state 2, 1.3; when referring to the third

page - goes to state 3, 1, 2.

With such an organization of the accumulator, priority control S of the memory hierarchy can be realized, and any deterministic deletion algorithm can be used as the strategy of the deletion algorithm.

Claims (2)

1. USSR author's certificate number 537386, cl. O 11 S 7/00, 1975. 2. Shigik A. G. et al. Digital computers. M., Saenergy, 1975, 5 (prototype).