SU693362A1 - Device for interfacing processor with input/output arrangement - Google Patents

Claims (2)

which are stored in the multiplex channel RAM. The UIC contains the memory address of the central processor and the information necessary for performing an I / O operation. Each external device has its own USK. When it is installed with this external device, its yCk is extracted in the PMAN in the general register of the USK, from which the exchange control is used. After the transfer of the USK information for this subscriber. It is transmitted back to the PFMC for storage. The transfer of the CCP to the PSCC in the USK register and back is spent several machine lines, which increases the time for establishing communication with an external device. In addition, this device for communication of the processor with I / O devices at each moment of time exchanges information with only one external device, which eliminates the possibility of the simultaneous operation of several speeds of external devices. Thus, the disadvantage of this device is low bandwidth. The aim of the invention is to increase the capacity of the device. The goal is achieved by introducing a subchannel into the device by the number of I / O devices, each of which contains a register of control words connected by a first input to a first output of a driver and a second and third outputs which are connected respectively to the KD input of the write register and the first input of the reading register, and the controlled counter of machine cycles, the output connected to the input of the driver of control signals, and, three The second output of the processor instruction processing unit and the second output of the communication register are connected respectively to the second and third tem input of the control word registers, the outputs of which are connected to the corresponding inputs of the data output unit, the fourth outputs of the control signal drivers of the subchannel signals are connected to the corresponding inputs from the group the inputs of the priority analysis block, the output of which is connected to the inputs of the controlled counters of machine cycles, the outputs of the write registers are connected to the corresponding inputs of the address output block, the third output of the communication register with the processor is connected to the second inputs of the subchannel reading registers, the second input of the recording register, the fifth input of the control transmitter and the output of the reading register of the i -th subchannel are the input and output of the 1 - OI group of inputs and device outputs. The drawing shows a block diagram of a device comprising an instruction processing block 1, a processor communication register 2, a mask register 3, a request register 4, a priority analysis block 5, an address issuing block 6, a data issuing block 7, a subchannel 8, a switching-on retnstra 9 control words, driver for control signals, record register 11, reading register 12, and a controlled clock counter 13, first 14, second 15 and third 16 device inputs, address 17 and information 18 device output and group 19 of inputs and device outputs for connecting devices and input-output. The device works as follows. In block I, input 14 receives instructions — the reception of a control word from the processor with an I / O device number code (YY). From the output of block 1, the control word prvem signal goes to register 2, and the signal, which is the decrypted WU number, goes to register 9 of the corresponding subchannel 8. On signals from block i, the control word for one subchannel goes through input 15 to register 2, and then to register 9 of the corresponding subchannel. During the transmission of the control word from the processor to the device, the operation of block 5 is blocked by a signal from block 1. The implementation of requests for input / output devices to exchange information is carried out in the same sequence. I / O device requests for data exchange are received at input 16 and register 4 associated with block 5. 1) and the presence of a control word for the subscriber initiated by a signal arriving at the corresponding input of block 5 on the driver 1O, and no signal is given request to register: 3, request is analyzed by block 5. As a result of the analysis, block 5 issues a standard {1 priority but a request & c that goes to the corresponding subchannel 8. 13 mshpishlh tpktoy and; - "1t its spool. The clock pulses of the counter will post-shaper the shaper 10, which controls rp (by the subchannel I.). Work in the read mode and in the ycTpoHCTfjo input and output memory as follows. A request from the subscriber through unit 5 retrieves the control counter 13. C shaper 10 The register 9 generates a signal allowing the control word register to output the memory address of the central computer to the input of the address block 6. From which the address goes to the processor output 17. The latter, receiving the address, selects information from the memory and exposes its input 15, otku yes she enters the register 2. Shaper U issues permission to register 12 to receive information. The information from register 2 is entered into register 12. Then, via outputs 19, information from register 12 and driver 1O is output to the corresponding input / output device. When writing to the processor, the I / O device exposes information to input 19 which, in the presence of an enable signal from the imaging unit 10, is written to the write register 11. Shaper 1O issues a signal to register 9 of the control word allowing the issuance of the memory address of the central calculator to block 6 and then to output 17 to the processor. The issuance of information from the register 11 is carried out through the data output unit 7. The block of indicators combines the excitation signals of the I / O devices, analyzing their state and transmitting them to the processor. Each of the I / O devices has direct access to the subchannel, where a control word is stored in register 9 and buffered in registers. information The presence in the subchannels of control counters of 13 machine cycles allows parallel and independent processing of requests from several I / O devices. Thus, the device provides a parallel exchange of information between the processor and several devices l fUflm mJPD that iipWfjonHT to increase the pass f; nof-o6ffocTR device. Claims of the Instance {interconnect processor interface with I / O devices, containing an instruction processing block 1, a processor connected to the first input of a communications register with a processor by a first output, the first output of which is connected via a mask register to the first input of a priority analysis block, the second and the third inputs of which are connected respectively to the output of the request register, and the second output of the processor instruction processing block whose inputs and the second input of the communications register with the processor are the corresponding inputs The device, the address output unit in the data output unit, the outputs, which are respectively the address and information outputs of the device, are characterized in that, in order to increase the capacity of the device, subchannels are entered in it by the number of input and output devices, each of which contains a control register Words connected by the first input to the first output of the control signal generator, the second and third outputs of which are connected respectively to the input of the write register and the first input of the reading register, and the control A machine clock counter, an output connected to the input of the control signal generator, the third output of the processor instruction processing unit and the second output of the communication register connected to the second and third inputs of the control word registers, respectively, whose outputs are connected to the corresponding inputs of the data output unit; the fourth the outputs of the control signal drivers of all subchannels are connected to the corresponding inputs from the group of inputs of the priority analysis block, the output of which is connected to the inputs of the controllable the machine clock counters, the outputs of the register of registers are connected to the corresponding input of the address issuing unit; in and out -t -th input group; and device outputs. Sources of information taken into account tfi expertise USSR certificate G06 F 15/16, 1969. USSR certificate GO6 F 3/04, 1973